Publications

Abstract : Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO2, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.