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Publication Type : Conference Paper
Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)
Source : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), IEEE, Kolkata, India (2019)
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract : Logic encryption for combinational circuits are proposed in this paper. Logic encryption is achieved by using key gate transistors in the circuit schematic of subtractors and adders. In this work, two logic encrypted full adder and subtractor circuits and half adder and half subtractor circuits using logic encrypted gates are designed and proposed. Of the two proposed circuits for adders and subtractors, one is strong logic encrypted than the other. All the encrypted adders and subtractors are compared with conventional adders and subtractors for logic encryption level and various other parameters like area and power. The results show improvement in area and power. The proposed half adder has 42% more area and 26.02% more power and half subtractor has 50% more area and 24.4% more power than the existing circuits. The proposed full adder has 25% less area (transistor count) and 33% less power consumption and the proposed full subtractor is also better in terms of area and power consumption with 30% and 24% lesser. Even strong logic encrypted full adder and full subtractor are proposed in this work. Full adder and subtractor have 22% increase in area each and on an average 2.3% increase in power each respectively.
Cite this Research Publication : K. Pritika and M. Vinodhini, “Logic Encryption of Combinational Circuits”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.