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Logic Obfuscation Technique for Securing Test Pattern Generators

Publication Type : Conference Paper

Publisher : Elsevier

Source : Proceedings of the 2nd International Conference on Electronics and Sustainable Communication Systems, ICESC 2021

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Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2021

Abstract : As the economic process of integrated circuit (IC) process proceeds, various supply chain components will copy ICs to introduce hardware Trojans, and overbuild ICs. A variety of hardware security studies have been conducted in order to prevent piracy, reverse engineering, and overbuilding through obfuscation. Obfuscating the design by arbitrarily inserting extra gates; solely an accurate key makes the design provide correct outputs. A hacker can decrypt the obfuscated design in an exceeding time rectilinear to the number of keys by observing the key values to the output. Nevertheless, these approaches provoke high overheads, and design obfuscation cannot give any security for the netlist of the third-party IP core (Intellectual Property). To avoid these vulnerabilities of hardware security approaches, this research work proposes a sensible logic obfuscation technique with low overheads to prevent a mortal from RE both the gate-level netlist and therefore the layout of IC and shield IC from piracy, and we then evolve techniques to mend this weakness and build obfuscation exponential within the range of inserted keys by designing the circuit through state diagrams in mentor graphics HDL designer tool.

Cite this Research Publication : Bhakthavatchalu Ramesh ,Sumanth, B. Naga, Naidu P. Shanmukha Naga, Koduri, Pavan Sri Ram, v, Somanathan, Geethu Remadevi,"Logic Obfuscation Technique for Securing Test Pattern Generators",

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