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Low-Complexity Systolic Design for Finite Field Multiplier

Publication Type : Conference Proceedings

Publisher : ICGCCEE

Source : International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 (2014)

Accession Number : 14666020

Keywords : Computer architecture, critical path, Delays, Digital arithmetic, Finite element analysis, Finite field, finite field multiplication, finite field multiplier, Flow graphs, Galois field, Galois fields, irreducible polynomial, low-complexity systolic design, operation latency, polynomial basis finite field multiplier, Polynomials, structure complexity, synopsys design vision, Systolic arrays, systolic design, systolic structure, Very large scale integration, Xilinx

Campus : Coimbatore

School : School of Engineering

Department : Electronics and Communication

Verified : Yes

Year : 2014

Abstract : Here focus, is to implement a polynomial basis finite field multiplier. An area efficient systolic structure for finite field multiplication over the galois field GF(2m) based on irreducible polynomial was introduced. A novel cutest retiming can be introduced to reduce the critical path and thereby reduce the latency of operation. From the synthesis result from synopsys design vision and Xilinx, we find that the complexity of structure in terms of area, power and latency of the proposed structure can be reduced from the existing design.

Cite this Research Publication : T. P. Rajalakshmi and Rajesh C. B., “Low-Complexity Systolic Design for Finite Field Multiplier”, International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), 2014. 2014.

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