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Low-power High-speed Approximate Multiplier Design Using Compression Techniques

Publication Type : Conference Proceedings

Publisher : Springer

Source : Microelectronics and Telecommunication Engineering

Url :

Campus : Bengaluru

School : School of Engineering

Year : 2023

Abstract : Approximate computing is a promising approach in digital circuit and digital signal processing applications which are implicit error tolerant circuits. In this project, four approximate multipliers are proposed with three approximate 4–2 compressors designs. To extend the applicability of the proposed approximate multiplier design highly configurable signed/unsigned multiplication is introduced using a high-level configuration parameter. Inner stage pipelining technique is used to maximize the operating speed with least path delay overhead which bring further improvements in performance efficiency, and optimal clock gating technique is used to reduce the power consumption rate, which bring improvement in energy efficiency. The proposed method was implemented in Xilinx ISE 14.7 version tool and synthesize in cadence genus tool with 45 nm technology. The four proposed multipliers are used in the application of image multiplication by discretizing image in MATLAB and Modelsim. As a result, the area, power, and delay were reduced from the exact multiplier, and the energy efficiency and performance efficiency is more when compared with the existing method.

Cite this Research Publication : Shayanki and Paramasivam C “Low-power High-speed Approximate Multiplier Design Using Compression Techniques”, 2023 6th International Conference on Microelectronics and Telecommunication Engineering, ICMETE 2022, Lecture Notes in Networks and Systems, Volume 617 LNNS.

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