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Mapping multi-loop nest algorithms on to reconfigurable architecture

Publication Type : Journal Article

Publisher : Journal of Artificial Intelligence

Source : Journal of Artificial Intelligence, Volume 5, Number 4, p.142-151 (2012)

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Campus : Coimbatore

School : School of Engineering

Department : Electronics and Communication

Verified : Yes

Year : 2012

Abstract : Recently, FPGA (Field Programmable Gate Arrays) technologies have made significant advances in both speed and capacity. Specifically, the design methodology to map the loop dependencies in a do loop algorithm on to a linear array of processors after extraction of parallelism is a challenging task. The mapping of Full Search Block Motion Estimation (FSBM) and edge detection algorithms are taken up here as they represent multi loop nested algorithms that are intensive in computations. Also, a method of prefixing the elements in the mapping vectors has been used which reduces the search space for both the algorithms. The formulation of a dependence vectors for the FSBM is explained and the architecture for the computationally intensive FSBM and Edge detection algorithm is developed and the simulation and synthesis results are presented. © 2012 Asian Network for Scientific Information.

Cite this Research Publication : B. Tripura B Sundari, “Mapping multi-loop nest algorithms on to reconfigurable architecture”, Journal of Artificial Intelligence, vol. 5, pp. 142-151, 2012.

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