Publications

Abstract : The need for placing more number of transistors in the core area by shrinking of electronic devices has brought out the necessity of scaling down the Field Effect Transistor (FET) devices. According to the current equation of existing MOSFET device the parameters which can increase the device current is probably channel width and the mobility of electrons and holes. The parameter which can help in improving the device performance will be the mobility of electrons and holes. Hence the necessity of replacing the channel material has become a leading research work in nano electronics. The allotrope of carbon atom - Graphene has the most required mobility range which can help in scaling down the currently available MOSFET devices. Some of the parameters which can be improved due to the replacement of channel material is the device drain current, reduction in the amount of impurity added to obtain the required drain current. A scaled down 15nm Dual Gate Graphene Field Effect Transistor is modeled in this work. As the device is scaled down to a such a narrow range the necessity of investigating the device parameters in a nano scale has been carried out using a novel approach of segmenting the channel. An additional focus in this paper is to employ a computationally efficient method for including the Quantum Capacitance effect. The most common methodology for obtaining the values for quantum capacitance is through solving the equations simultaneously as proposed in [1],[2]. The parameters of interest like quantum capacitance and channel potential are assumed initially and the equations are solved until the assumed parameter value and the obtained value are equal. This not only increases the simulation time but also ends up in approximate result values which are complex. The complex solutions cannot be separated into a real and imaginary value in verilog-a as well as in verilog-ams language as given in [3],[4], to enable circuit compatibility. Moreover the approximate results obtained through the existing methodologies are of huge margin for a 15nm scaled down device. This makes it difficult to implement dual gate GFET in cadence - virtuoso environment. Hence the only way to implement the equations in a circuit level of simulation is to bring out the results as real value and not a complex number. In order to avoid complex solutions the only way is to convert the equations into a polynomial. Hence a novel method which uses a fourth order polynomial known as quartic equation in which the quantum capacitance is derived from the channel potential equation is proposed. The methodology adopted in this work is quartic equation whose results are real valued solutions and hence overcomes the complex number solutions obtained so far. This makes it possible for the model to be developed in verilog-a and incorporated as circuit model. The proposed fourth order polynomial equation can be used to calculate quantum capacitance for any device which obeys the ballistic transport. Hence the device structure proposed in this work is limited to ballistic structure. Ballistic transport of electrons can be obtained when the length and width of the channel is lesser than the mean free path. A N-type impurity of about 2.63-1011cm-2 (calculated, not presented here) is added in order to achieve a mobility of 2497 cm/Vs. Impurities can be further added but it will lead to increased scattering of electrons which will affect the ballistic structure. Hence further addition of impurity to enhance the mobility is stopped. In this model the carriers' Fermi velocity of 106 m/s, tox of 1.5nm (top and bottom), length (L) of 15nm, a width (W) of 150 nm, Cox(bottom gate) of 23.024×10-3 F/m are used and the determined value of mobility is found to be better as reported in Table 1. © 2017 IEEE.