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Publication Type : Conference Paper
Publisher : ICCPCT
Source : 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) (2017)
Keywords : Adders, Area-efficient, arithmetic functions, Carry logic, carry select adder, Computer architecture, Computers, data processing processors, delay, Delays, Digital arithmetic, integrated circuit design, Logic design, Logic gates, Low-Power, Modified CSLA, Multiplexing, SQRT CSLA, Very large scale integration, VLSI, VLSI system design
Campus : Coimbatore
School : Department of Electronics and Communication Engineering, School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Year : 2017
Abstract : The factors which play a pivotal role in VLSI system design are power, delay and area. In order to carry out fast arithmetic functions in many data processing processors, Carry Select Adders (CSLAs) are widely used because they are one amongst many of the fast adders that could be used for the high speed data processing. CSLAs stand out from the remaining conventional adders in terms of performing faster operations. The scope for reduction in area can be observed from the structure of CSLA. Hence a gate level modification has been proposed for the regular CSLA. Based on this modification 16-b, 32-b, 64-b and 128-b SQRT CSLA has been designed. Parameters such as area, power and delay have been analyzed and compared with the regular SQRT CSLA. The comparison between regular and modified CSLA showed a reduction in area and power. This work proposes the use of simple, optimized and an efficient gate-level modification to significantly reduce the area and power of carry select adder with a slight increase in delay.
Cite this Research Publication : T. Abhiram, Ashwin, T., Sivaprasad, B., Aakash, S., and Dr. Anita J. P., “Modified Carry Select Adder for Power and Area Reduction”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.