Publication Type : Journal Article
Publisher : Proceedings on IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)
Source : Proceedings on IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Volume 1, p.2201-2203 (2016)
Campus : Bengaluru
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Verified : Yes
Year : 2016
Abstract : Most signal processing applications that uses real valued signals are designed and implemented using Fast Fourier algorithms. The imaginary parts of butterflies are scheduled in place of repeated operation for radix-23 and radix-24 butterfly structures to deal with the hybrid data path. Along with this scheduling technique folding methodology is used to reduce the redundant samples in the real valued signals. hardware complexity is reduced by using Multiple Delay Commutator (MDC) architecture for parallel samples. As a result of this butterfly structure, hardware complexity, area, power and delay is greatly reduced and the throughput is increased
Cite this Research Publication : V. Suganya and Paramasivam C., “Parallel pipelined FFT architecture for real valued signals”, Proceedings on IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), vol. 1. pp. 2201-2203, 2016.