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Publication Type : Journal Article
Publisher : Elsevier B.V.
Source : Microprocessors and Microsystems, Embedded Hardware Design, Elsevier B.V., Volume 65, p.47-56 (2019)
Keywords : Address generators, Application specific integrated circuits, Computer hardware, Computer software, Field programmable gate arrays (FPGA), Hardware, Hardware complexity, IEEE Standards, Implementation complexity, integrated circuit design, Interleavers, Logic synthesis, Mobile telecommunication systems, Operating frequency, Reconfigurable, Reconfigurable architectures, Reconfigurable hardware, Resource utilizations, Software simulation, Turbo codes, Wireless local area networks (WLAN), Wireless telecommunication systems
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Verified : No
Year : 2019
Abstract : This paper presents low-complex and novel techniques for designing reconfigurable architectures for multi-standard address generator and interleaver. The emphasis of this work is on hardware re-use, but it also focuses on optimizing the hardware to support multiple standards. A low-cost reconfigurable architecture for address generator and interleaver is proposed which operates in WLAN (802.11a/b/g and 802.11n), WiMAX (802.16e) and 3GPP LTE standards. A simple algorithm and a reconfigurable architecture that eliminates the computationally intricate mod function for LTE, and floor as well as mod function for WLAN/WiMAX, are proposed to reduce the hardware cost as well as implementation complexity. Novel architectures are also proposed to select the increment values for 16-QAM and 64-QAM schemes. A unique configurable subtracting sub-block for each modulation scheme is also presented. Software simulation is carried out to authenticate the functionality of the algorithm. The proposed reconfigurable architectures are realized on FPGA and tested on board. Synthesis results on Spartan-3 FPGA display 66% reduction in FPGA resource utilization and 74% increase in operating frequency compared to the cited address generators. Implementation results on Kintex UltraScale FPGA display a reduction of 34% in resource utilization and 20% in total on-chip power compared to the cited interleavers. This design is also implemented using 45 nm CMOS standard cell technology, and ASIC synthesis results of the reconfigurable address generator exhibit 76.4% improvement in data rate and 52.23% decrease in latency compared to the state-of-the-art address generators. The proposed multimode interleaver also exhibit 60.28% reduction in hardware complexity. © 2018 Elsevier B.V.
Cite this Research Publication : Geethu S. and Gopalakrishnan, L., “Reconfigurable address generator for multi-standard interleaver”, Microprocessors and Microsystems, vol. 65, pp. 47-56, 2019.