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Reliable Low Power NoC Interconnect

Publication Type : Journal Article

Publisher : Microprocessors and Microsystems

Source : Microprocessors and Microsystems, Elsevier B.V., Volume 57, p.15-22 (2018)

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Keywords : Analytical models, Codes (symbols), Computer architecture, Distributed computer systems, Electromagnetic pulse, Error control code, Error correction, Error correction capability, Error detection, Error-correcting, Errors, Hamming code, Integrated circuit interconnects, Inventory control, Multi core and many cores, Network-on-chip, On-chip interconnects, Performance estimation, Programmable logic controllers, Random errors, Reliable data transmission, Routers, Servers, System-on-chip

Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Year : 2018

Abstract : Information communicated through Network on Chip (NoC) in System on Chip (SoC) is highly prone to different sources of noise, like coupling, radiation and electromagnetic interference. The outcome is multi-bit errors, which can either be random or burst. As the demand for reliable NoC increases, optimal error correcting coding techniques become imperative for SoC and various multi-core and many-core architectures. A novel Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB) is proposed to achieve reliable data transmission through NoC. The proposed technique corrects burst error of four bits or random error of eleven bits or combined burst and random errors of total four bits for an input flit size of 32 bits. Analytical model based performance estimation for coding technique is extensively used in NoC. Reliability, link swing voltage and link power consumption are estimated using analytical model for the proposed MECCRLB coding technique. All the results obtained for MECCRLB coding technique are compared with Hamming product code with Type II HARQ. Estimated results show that at a probability of residual error of 10−25, the link swing voltage and the link power are reduced by 30% and 75% respectively. Results obtained from simulation followed by synthesis indicate that there is a reduction of 65%, 44%, 27%, 28% and 49% in bit overhead, NoC router area, NoC router power, codec power and codec area respectively. Furthermore, MECCRLB coding technique achieves higher error correction capability and reduces the need for retransmission. This signifies that the proposed coding technique outperforms Hamming product code with Type II HARQ in reliability, area and power. © 2017 Elsevier B.V.

Cite this Research Publication : M. Vinodhini and Dr. N.S. Murty, “Reliable low power NoC interconnect”, Microprocessors and Microsystems, vol. 57, pp. 15-22, 2018.

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