Back close

Statistical Viability Analysis and Optimization through Gate Sizing

Publication Type : Journal Article

Publisher : Springer, Singapore

Source : Lecture Notes in Electrical Engineering, Springer Verlag, Volume 475, p.149-155 (2018)

Url :

ISBN : 9789811082399

Keywords : Delay circuits, Electric network analysis, False paths, Gate sizing, Gates (transistor), Integrated circuit manufacture, Integrated circuit testing, SSTA, Static sensitization, Statistical methods, Timing devices, Viability

Campus : Coimbatore

School : School of Engineering

Center : Electronics Communication and Instrumentation Forum (ECIF)

Department : Electronics and Communication

Year : 2018

Abstract : When the technology of VLSI circuits scales down to nanometer region, the parameter variation has a great impact on the circuit performance. Traditional false path filtering methods which use normal corner-based timing analysis miss some of the critical false paths or true paths. Viability analysis is one of the most accurate methods for false path filtering. Statistical timing analysis, which models the parameter variation statistically, becomes a promising variation-aware solution in the digital circuit design at the nanometer era. Thus, statistical viability analysis improves the accuracy in finding false paths or true paths in a design. For further optimization, the concept of gate sizing is used along with viability analysis. The criticality for gate selection is evaluated through viability analysis. The analysis and optimization are carried out on ISCAS 85 benchmark circuits. For a sample circuit C2670, a delay reduction of 10.99% is obtained with a slight increase in power of 0.65% and area overhead of 0.63%.

Cite this Research Publication : K. Sreenath and Ramesh S. R., “Statistical Viability Analysis and Optimization through Gate Sizing”, Lecture Notes in Electrical Engineering, vol. 475, pp. 149-155, 2018.

Admissions Apply Now