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The MUX-Based PUF Architecture for Hardware Security

Publication Type : Conference Proceedings

Publisher : IEEE

Source : 2021 International Conference on Circuits, Controls and Communications (CCUBE)

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Keywords : Field Programmable Gate Array (FPGA),Hardware Security,IOT,MUX-PUF,Physical Unclonable Function (PUF),Post implementation timing simulation

Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Year : 2021

Abstract : In the world of Internet of things (IoT), Hardware security plays very important role. Hardware security is a vast area, in which Physical Unclonable Function (PUF) is apart of it. PUF works on the concept of manufacturing process variations. Designing the PUF is easy but replicating the same design is harder, so it is best suitable for generating the unique response with the random challenges. Due to uncontrolled process variation, the unique responses (output) are generated by PUF. These unique response are used as finger print of the IC's. It is difficult to access the data from IC's by unauthorized person after employing the PUF as a security primitive. Applications of PUF in the literature are True Random Number Generation, Identification, Authentication and IP protection. This paper presents, design and implementation of different MUX based PUF architectures, post implementation timing simulation and comparing the resources utilization of the Arbiter PUF, Feed-Forward PUF and Double Feed-Forward XOR Arbiter PUF on the ZYNQ 7000 FPGA board using the VIVADO 2019.1 software.

Cite this Research Publication : K. Hatti and C. Paramasivam, "The MUX-Based PUF Architecture for Hardware Security," 2021 International Conference on Circuits, Controls and Communications (CCUBE), 2021, pp. 1-7, doi: 10.1109/CCUBE53681.2021.9702737.

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