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Publication Type : Book Chapter
Publisher : Recent Trends in Communication Networks, IntechOpen, (WoS/Book SCI),
Source : Recent Trends in Communication Networks, IntechOpen, (WoS/Book SCI), IntechOpen Limited, United Kingdom (2019)
Keywords : Clock gating, Inductive Noise, Power Supply Noise, Resistive Noise, Variable Frequency Clock
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2019
Abstract : The on-chip activities of any modern IC are always inhibited due to the occurrence of power supply noise (PSN) in the chip power line. From many decades, researchers are pondering on what are the major issue of this PSN occurrence and how it can be suppressed without interfering the actual chip functioning. In the course of time, it is found that the uncontrolled triggering of the on-chip system clock and the unguarded on-chip power line is instigating the two major factors for the occurrence of PSN i.e., i(t) → instantaneous current and di/dt → current ramp or the rate of change of current over time. Both i(t) and di/dt are also the sub-factors to rise the PSN components like resistive noise and inductive noise respectively. In this chapter, we light upon the occurrence of resistive and inductive noise as well as depict their individual impact on the PSN occurrences. There is also discussion on how PSN is suppressed over the years in spite of facing challenges in the execution of suppression techniques. This chapter even concludes on the suitable ways for mitigating PSN in the contemporary era of delivering complex on-chip features.
Cite this Research Publication : Dr. Pritam Bhattacharjee, Prerna Rana, and Alak Majumder, “Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges”, in Recent Trends in Communication Networks, IntechOpen, (WoS/Book SCI), United Kingdom: IntechOpen Limited, 2019.