Qualification: 
Ph.D, M.Tech
i_mamtha@blr.amrita.edu

Dr.Mamatha I., is currently working as Assistant Professor in the Department of Electrical and Electronics Engineering. She joined Amrita School of Engineering, Bengaluru in the year 2006 before which she served in teaching role in many academic institutions. She has 21 years of rich experience in teaching and is passionate about teaching.

Dr.Mamatha holds Ph.D Degree in Engineering from Amrita Vishwa Vidyapeetham and has several peer reviewed journal and conference publications to her credit.

Education

  • 2018: Ph.D. in Engineering (Area: VLSI Signal Processing)
    From: Amrita Vishwa Vidyapeetham
  • 2010: M.Tech. in VLSI Design
    From: ASE, Bengaluru, Amrita Vishwa Vidyapeetham
  • 1999: B.E. in Electrical and Electronics Engineering
    From: KVGCE, Sullia, Mangalore University

Professional Appointments

Year

Affiliation

January 2006-Present

Assistant Professor, Amrita School of Engineering, Bengaluru

August 2005-December 2005

Lecturer, Don Bosco Institute of Technology, Bengaluru

August 2004-July 2005

Lecturer, The Oxford College of Engineering, Bengaluru

October 2000-July 2004

Lecturer, NRAMPT, Nitte, Karkala Taluk, Udupi District

September 1999-September 2000

Lecturer, KVGCE, Sullia, D.K

Major Research Interests

  • Her research interests include developing efficient VLSI architectures for signal/image processing applications with main focus on minimization of algorithmic and architectural complexity of structures. Her other area of interests include digital controller design for power electronic applications, implementing IoT applications on hardware platforms, development of smart devices using smart technology, wireless power transmission, optimization of lossess in microgrid and fiber optic sensor based soft robotic arm.

Membership in Professional Bodies

  • Member-IEEE

Publications

Publication Type: Conference Proceedings

Year of Publication Title

2021

M. Mohith K. Reddy, D. Rohith, V. Krishna, C. Reddy, A., and Mamatha, I., “Smart Helmet using Advanced Technology”, Information and Communication Technology for Intelligent Systems. Springer Singapore, Singapore, pp. 479–488, 2021.[Abstract]


There has been increasing number of motor bike accidents reported during last few years, and rider's negligence happens to be one major reason for the same. In this work, a smart helmet with features for the safety of the rider is proposed. Three major features are embedded in the present work such as avoidance of driving without helmet, avoidance of drunk and drive, and accident detection and intimation. A force-sensing resistor (FSR) is used for detecting the presence of helmet which controls the access to the vehicle. This feature is useful even to prevent motorcycles from being stolen. An alcohol detector placed within the helmet senses the limit of alcohol consumption by the rider and restricts the vehicle access in case limit exceeds. Accident intimation to the rescue department and to the family of the rider is the third feature in the proposed work. The hardware is built having all these features and is tested in a laboratory environment.

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2019

M. Nair, Mamatha, I., and Tripathi, S., “Distributed arithmetic based hybrid architecture for multiple transforms”, Lecture Notes in Electrical Engineering, vol. 526. Springer Verlag, pp. 221-232, 2019.[Abstract]


Eight-point transforms play an important role in data compression, signal analysis and signal enhancement applications. Most widely used transforms of size -8 are Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT), Discrete Sine Transform (DST), and Discrete Fourier Transform. There have been applications requiring multiple transforms for improving the performance. Unified/Hybrid architectures supporting multiple transforms is a possible solution for such demands as independent architecture for each transform requires more resources and computation power. In this work, a Distributed Arithmetic (DA) based multitransform architecture for supporting 1-D 8-point DCT, DFT, DST and DWT is proposed. A multiplier-less architecture leading to reduced hardware is implemented in 45 nm CMOS technology in Cadence RTL compiler as well as on FPGA using Xilinx ISE. Compared to the standalone transform architectures, there is 51.2% savings in number of adders, 44.34% saving in Look Up Table (LUT) utilization and 54.18% savings in register utilization in the proposed architecture. © Springer Nature Singapore Pte Ltd. 2019.

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2018

D. Devipriya, V. Sri, S., and Mamatha, I., “Smart Store Assistor for Visually Impaired”, 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, Bangalore, India, pp. 1038-1045, 2018.[Abstract]


Visual impairment is one of the disabilities of a human being. To date, numerous methods have been proposed to enhance the life style of visually impaired and blind people. Still, purchasing products in the supermarket without others support is tricky one for them. In this work, a Smart Store Assistor for visually impaired people is proposed. Three major concerns such as locating the product, identifying product and buying the product are addressed in this work. The System consists of 3 modules namely Product Identifier, Smart Glove and Smart Trolley. Radio Frequency Identification Technology (RFID) is used to identify the products. In Product Identifier module, a buzzer will ring whenever the required product is located. Smart Glove module is used to scan the product where an audio instruction will detail about the product specifications to the buyer. Further, when the product is placed in the cart, an automated billing system will provide final bill of the purchased products. Design and hardware implementation of the working prototype model has been demonstrated in the proposed work.

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2018

J. Laxman Pakhale and Mamatha, I., “Comparative Study of Different Current Control Techniques for Single Phase Grid Integrated Photovoltaic System”, 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, Bangalore, India, pp. 1259-1266., 2018.[Abstract]


In this paper, design, analysis and control of single phase grid connected photovoltaic system is proposed. Basically two controllers are associated with this system. First, maximum power is extracted from photovoltaic system by using input side MPPT controller and second, grid side controller which performs DC-link voltage control and injecting harmonic free current into the grid. The main objective is to control grid current with the help of controllers for which current controller of grid must follow sinusoidal reference synchronized with grid voltage. A comparative study between Proportional Integral current controller, Hysteresis current controller and Predictive current controller is done for single phase grid integrated photovoltaic system with the help of MATLAB/Simulink software. The performance of all three controllers are examined and compared with the help of their performance. Simulation results demonstrated that predictive current controller gives fast response, minimum distortion and good reference tracking when compared with other two controllers.

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2017

I. Mamatha, Tripathi, S., and Sudarshan, T. S. B., “Convolution based efficient architecture for 1-D DWT”, 2017 International Conference on Computing, Communication and Automation (ICCCA). IEEE, Greater Noida, India, 2017.[Abstract]


In this work, a high throughput architecture for 1-D Discrete Wavelet Transform is proposed. The work proposes DWT computation through convolution of a `M' point input sequence with a `L' tap wavelet coefficients. Computation of DWT of an N point sequence is carried out by summing the results of blocks of `M' points. For illustration, an 8 tap filter and block size of 4 is considered. Through poly-phase filter structure and simple processing elements, effective computation is achieved. Architecture is 100% efficient in terms of hardware utilization and has an improved throughput of two fold. Xilinx ISE tools are used to carry out functional simulation and implementation. The proposed architecture can work at a maximum frequency of 398.25MHz while implementing on Virtex4 xc4vlx15-10sf363 target device.

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2017

A. P. Asokan and Mamatha, I., “A novel approach to wireless power transfer”, 2017 International Conference on Technological Advancements in Power and Energy ( TAP Energy). IEEE, Kollam, India, 2017.[Abstract]


The fundamental capacity of Wireless Power Transfer (WPT) is to permit electrical gadgets to be persistently charged and conquer the requirement of a power line. Remote power can be bridled and actualized in a home to such an extent that a portable PC and telephone gets charged persistently and remotely without the requirement for connecting anything to. In this paper, an inductive wireless power charging system to charge a laptop at 19.5V, 2.3A is proposed. An ac-ac resonant converter is adopted at the front end instead of a dc link. An LLC-SS is employed to reduce the power loss during transmission. The main challenge in WPT system lies in designing efficient transmitter and receiver coils and maintaining a constant voltage at the load for varied distance between the coils. A PI controller is adapted to mitigate the effects of variation in mutual coupling. Resonant coupling will improve the system efficiency and permit the power transfer at kilohertz frequency range.

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2016

K. Gopinathan and Mamatha, I., “Average current mode controlled DC - DC converter using digital controllers”, 2016 Biennial International Conference on Power and Energy Systems: Towards Sustainable Energy (PESTSE). IEEE, Bengaluru, India, 2016.[Abstract]


A current fed push pull converters cascaded with a buck pre-regulator is proposed. Voltage stress of the push pull switches is reduced by buck pre regulation. Pulse width modulation is done only to the switch in buck stage. Output voltage and the buck inductor current is controlled using average current mode control. The closed loop simulation of a 20W,100V,0.2A cascaded buck push pull converter with analog control circuit is done using PSIM. Closed loop simulation using digital control circuit is done by using a SIMCOUPLER module which couples power electronic circuit in PSIM and digital control circuit in MATLAB. Further, hardware implementation of digital controllers on two platforms is explained. Switching pulses are generated using digital circuit are fed to the converter switches and the converter is tested for the open loop operation.

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2016

I. Mamatha, Dr. Shikha Tripathi, and TSB, S., “Pipelined architecture for filter bank based 1-D DWT”, 2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2016.[Abstract]


A Convolution based parallel and pipelined architecture using MAC Loop Based Filter (MLBF) is proposed in this work. The proposed modification to the MLBF structure produces one output sample for every clock cycle as compared to the MLBF structure which produces two outputs for every four clock cycles. This results in a speed up of 2× which is significant for processing real time signals of long length. Compared to the existing MLBF based 1-D DWT architecture, proposed design uses additional 8 multipliers and 8 adders. The proposed structure is independent of the input size and filter length and performs better than other architectures with same or less area utilization. Generality, scalability, high efficiency of hardware utilization are the other merits of the proposed structure. The architecture is synthesized on Virtex 6 xc6vcx240t-2ff784 FPGA board and can operate at a maximum frequency of 633.43 MHz. The frequency of operation is twice as that of the existing approach.

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2016

T. Rohith, Samhitha, V. S., and Mamatha, I., “Wireless Transmission of Solar Power using Inductive Resonant Principle”, 2016 - Biennial International Conference on Power and Energy Systems: Towards Sustainable Energy, PESTSE 2016. Institute of Electrical and Electronics Engineers Inc., 2016.[Abstract]


In this paper, wireleb transmibion of electric power using inductive resonating principle is proposed. Power from solar PV is considered as the source of supply. Comparison of the inductive resonance principle and inductive coupling principle of wireleb power transmibion is carried out. It is observed that efficient transmibion of power at lower frequencies can be achieved using resonance principle with high Q factor transceiver coils. The complete system is designed and implemented on the hardware developed. Input to the circuit is 30V, 0.12A from solar PV and a load of 5V,500mA cell phone is charged by the circuit developed. Overall power efficiency of 69.4% is achieved practically for the wireleb power transmibion using the proposed design at a transmibion frequency of 241kHz and at a distance of 8cm. The transmibion efficiency was found to be approximately 100% at the above mentioned frequency and distance.

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2015

K. Gopinathan and Mamatha, I., “Pre-regulated Push Pull Converter for Hybrid Energy Systems”, Advancements in Power and Energy (TAP Energy), 2015 International Conference on. IEEE, 2015.

2015

S. V. B. Bala Sai, Mamatha, I., Dr. Shikha Tripathi, and Sudarshan, T. S. B., “Modified MLBF based architecture for 1-D DWT”, 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC). IEEE, Madurai,India, 2015.[Abstract]


This work proposes an architecture for fast computation of 1-D Discrete Wavelet Transform (DWT). Existing MAC loop based filter (MLBF) is modified and a poly-phase structure for 1-D DWT is proposed. Proposed structure improves the throughput by 1.5x while using almost double the hardware as that of the existing structure. 1-D DWT using existing MLBF structure and proposed structure are simulated using ModelSim and synthesized using Xilinx ISE 14.2 on Virtex-6 XC6VCX240T-2FF784 target device. It is observed that the proposed architecture can be operated at a maximum frequency of 163.59MHz. The simulation results obtained from ModelSim is compared with MatLab R2010a output and found to be accurate.

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2015

I. Mamatha, Raj, J. N., Dr. Shikha Tripathi, and Dr. T.S.B. Sudarshan, “Systolic architecture implementation of 1D DFT and 1D DCT”, 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015. Institute of Electrical and Electronics Engineers Inc., 2015.[Abstract]


Discrete Fourier Transform is widely used in signal processing for spectral analysis, filtering, image enhancement, OFDM etc. Cyclic convolution based approach is one of the techniques used for computing DFT. Using this approach an N point DFT can be computed using four pairs of [(M-1)/2]-point cyclic convolution where M is an odd number and N=4M. This work proposes an architecture for convolution based DFT and its FPGA implementation. Proposed architecture comprises of a pre-processing element, systolic array and a post processing stage. Processing element of systolic array uses a tag bit to decide on the type of operation (addition/subtraction) on the input signals. Proposed architecture is simulated for 28 point DFT using ModelSim 6.5 and synthesized using Xilinx ISE10.1 using Vertex 5 xc5vfx100t-3ff1738 FPGA as the target device and can operate at a maximum frequency of 224.9MHz. The performance analysis is carried out in terms of hardware utilization and computation time and compared with existing similar architectures. Further, as the convolution based DCT has two systolic arrays similar to that of DFT, a unified architecture is proposed for 1D DFT/1D DCT. © 2015 IEEE.

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2014

I. Mamatha, ShikhaTripathi,, TSB, S., and Bhattar, N., “Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product”, Advances in Intelligent Systems and Computing. Springer, 2014.[Abstract]


A generic 2D systolic array for N point Discrete Fourier Transform using triple matrix product algorithm is proposed. The array can be used for a non power of two sized N point DFT where N=N1N2 is a composite number. It uses an array of size N2×(N1+1) which requires(2N+4N2) multipliers. For a DFT of size 4N2 (i.e multiple of four), an optimized design which requires 4N2 number of multipliers is proposed. It is observed that the proposed optimized structure reduces the number of multipliers by 66.6% as compared to the generic array structure while maintaining the same time complexity. Two examples are illustrated, one with non power of two size DFT and another with a DFT of size 4N2. Both the generic and optimized structures use the triple matrix product representation of DFT. The two structures are synthesized using Xilinx ISE 11.1 using the target device as xc5vtx240t-2ff1759 Virtex-5 FPGA. The proposed structure produces unscrambled stream of DFT sequence at output avoiding a necessity of reordering buffer. The array can be used for matrix -matrix multiplication and to compute the diagonal elements of a triple-matrix multiplication.

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2013

I. Mamatha, J Raj, N., Dr. Shikha Tripathi, and Sudarshan, T. S. B., “Reduced Complexity Architecture for Convolution Based Discrete Cosine Transform”, Electronic System Design (ISED), 2013 International Symposium on. IEEE, 2013.[Abstract]


Discrete Cosine Transform is a popular transform used in signal/image processing applications. Reduction in complexity of hardware architecture for the computation of DCT using the convolution based algorithm is proposed. An N point DCT can be computed through 2 pair of [(M-1)/2] point cyclic convolutions where M is an odd number such that N=2M. The proposed architecture uses only a pair of systolic array where inputs are pipelined against the one in literature where 2 pairs of systolic arrays are used. One of the systolic arrays uses processing element with tag bit and the other one does not need a tag bit. The architecture uses 50% less number of processing elements with just an additional increase in computation time by one unit. The architecture is divided into three stages as preprocessor stage, compute stage where a systolic array computes the cyclic convolution and a post processing stage to process the output of the systolic array to get the actual DCT output. It is observed that the proposed architecture has a reduction of about 42%adders and 64% multipliers as compared to the one in literature. Further, the architecture is simulated in ModelSim 6.5 and synthesized using Xilinx ISE10.1using Vertex 5 FPGA as the target device. The simulation results are matched favourably with that of the output obtained by MATLAB R2010a with MSE of1.3861x10-4.

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Publication Type: Journal Article

Year of Publication Title

2016

L. M P, Reddy, N. Kumar, S Rao, J., V Sudev, N., and Mamatha, I., “Wireless Power Transmission: A Simulation Study”, International Journal of Control Theory and Applications, vol. 9, pp. 179-188, 2016.

2015

I. Mamatha, TSB, S., Tripathi, S., and Bhattar, N., “Triple-Matrix Product-Based 2D Systolic Implementation of Discrete Fourier Transform”, Circuits, Systems, and Signal Processing, vol. 34, 2015.[Abstract]


Realization of \(N\) -point discrete Fourier transform (DFT) using one-dimensional or two-dimensional systolic array structures has been developed for power of two DFT sizes. DFT algorithm, which can be represented as a triple-matrix product, can be realized by decomposing \(N\) into smaller lengths. Triple-matrix product form of representation enables to map the \(N\) -point DFT on a 2D systolic array. In this work, an algorithm is developed and is mapped to a two-dimensional systolic structure where DFT size can be non-power of two. The proposed work gives flexibility to choose \(N\) for an application where \(N\) is a composite number. The total time required to compute \(N\) -point DFT is \(2(N_{1}-1)+N_{2}+N\) for any \(N=N_{1}N_{2}\) . The array can be used for matrix-matrix multiplication and also to compute the diagonal elements of triple-matrix multiplication for other applications. The proposed architecture produces in-order stream of DFT sequence at the output avoiding need for reordering buffer. Large sized DFT can be computed by repeatedly using the proposed systolic array architecture.

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2012

Dr. K. Deepa, ,, Mamatha, I., and kumar, D. M. Vijaya, “Digital Simulation of SISO-ZVS-Push pull Quasi Resonant Converter for Different Loads”, International Journal of Engineering Research and Applications (IJERA), vol. 2, no. 4, pp. 896–901, 2012.

Publication Type: Conference Paper

Year of Publication Title

2016

V. Chandran, Mamatha, I., and Tripathi, S., “NEDA Based Hybrid Architecture for DCT—HWT”, in VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016 International Conference on, 2016.

Publication Type: Book Chapter

Year of Publication Title

2014

I. Mamatha, Dr. Shikha Tripathi, Sudarshan, T. S. B., and Bhattar, N., “Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product”, in Advances in Signal Processing and Intelligent Recognition Systems, Springer, 2014, pp. 311–322.[Abstract]


A generic 2D systolic array for N point Discrete Fourier Transform using triple matrix product algorithm is proposed. The array can be used for a non power of two sized N point DFT where N=N1N2 is a composite number. It uses an array of size N2×(N1+1) which requires(2N+4N2) multipliers. For a DFT of size 4N2 (i.e multiple of four), an optimized design which requires 4N2number of multipliers is proposed. It is observed that the proposed optimized structure reduces the number of multipliers by 66.6% as compared to the generic array structure while maintaining the same time complexity. Two examples are illustrated, one with non power of two size DFT and another with a DFT of size 4N2. Both the generic and optimized structures use the triple matrix product representation of DFT. The two structures are synthesized using Xilinx ISE 11.1 using the target device as xc5vtx240t-2ff1759 Virtex-5 FPGA. The proposed structure produces unscrambled stream of DFT sequence at output avoiding a necessity of reordering buffer. The array can be used for matrix -matrix multiplication and to compute the diagonal elements of a triple-matrix multiplication.

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Courses Taught

  • Basic Electrical Engineering
  • Electric Circuit theory/Network Theory
  • Microprocessor
  • Transmission and Distribution
  • Utilization of Electrical energy
  • Communication Theory
  • Electrical Measurements and Instrumentation
  • Electromagnetic Theory
  • Signals and Sytems
  • Digital Signal Processing
  • Digital Systems
  • FPGA based System Design
  • Signal and Image Processing
  • VLSI Circuit Design
  • Analog Signal Processing and Control
  • Digital System Design
  • Hardware Software Co Design

Student Guidance

Undergraduate Students

Sl. No.

Name of the Student(s)

Topic

Status – Ongoing/Completed

Year of Completion

1

A. Sreeja Reddy

A.Jagadeesh

S. Praneeth Varma

Smart Device for Power Theft Detection and Power Sharing at Domestic Utilities

Ongoing

2021

2

P. Surya Kumar

P. Supraja

P. Chaithanya

Voice Transmission through Light

Completed

2020

3

K. Srujan

N. Hema Sundari

P. Nireesha

Self Powered Automatic Railway mobile Platform without using Staircase

Completed

2020

4

D. Devipriya

V. Sushma Sri

Smart Store Assistor

Completed

2018

5

V.Sushma Sri

Adaptive Restbus Simulation for Different EPS w.r.t Diagnostic Testing

( Internship)

Completed

2018

6

C.Akash Reddy

K. Muni Mohith Reddy

D. Venkata Krishna Rohith

Smart Helmet with Advanced Technology

Completed

2017

7

M.Likhith

P.Naveen Kumar Redy

S.Jagadeeswara Rao

V.Nirmith Sudev

Wireless Transfemission of of Power using Inductive Resonance Principle

Completed

2016

8

Fateh Raj Singh

Thodupunuri Rohith.

Vellore Sasi Samhitha

WirelessTransfer of Solar power using Inductive Resonating Principle

Completed

2015

9

Shravani M.

Namitha K

Shashank D.

Rishu Sharma

Fault Detection and Battery Management of a Mobile Robot

Completed

2012

10

J.Aswin Kumar

Nithin Mohan

Sanjeev Prakash

Sreejith V.Nair

Speed Control

of 3 Phase Induction Motor using ATMEGA644P

Completed

2011

11

Karan Rawat

Laxmi Nair

Nimisha Madhusoodanan

Sneha Suresh

Voice Recognition Security System

Completed

2010

12

Amal Roy, 

Anusmita Datta, Nishan D. Madtha, Priyanka Shekar

Rahul M. Nair, Revindra Sai Murali S.

Mobile Surveillance and Reconnaissance System

Completed

2010

Postgraduate Students

Sl. No.

Name of the Student(s)

Topic

Status – Ongoing/Completed

Year of Completion

1

K. Phani Raghavendra Sai

Multi Transform Architecture supporting AVC and HEVC Video Codec

Ongoing

2021

2

Jyoti Laxman Pakhale

Comparative Study of Different Current Control Techniques for Single Phase Grid Integrated Photovoltaic System

Completed

2018

3

Meghna Nair

Distributed Arithmetic based Hybrid Architecture for Multiple Transforms

Completed

2017

4

Athira Asokan

Closed Loop Wireless Charging System for Portable Devices

Completed

2016

5

Krishna Gopinathan

FPGA Based Cascaded Buck Push-Pull Converter

Completed

2015

6

Vidya Chandran

Hybrid Architecture for DCT-DWT

Completed

2015

7

Bala Sai SVB

An Efficient Reconfigurable Architecture for 1-D and 2-D DWT

Completed

2014

8

Anjana N.S.

Unified Systolic Array Architecture for 1D-DFT and 2D-DFT for Signal/Image Processing Applications

Completed

2013

9

Nikhitha Raj J

Reconfigurable Systolic Array Architecture for 1D DFT and 1D DCT for Signal/Image Processing Applications

Completed

2013

10

Tissy Thomas

Implementation of Single Input Fuzzy Logic Controller on FPGA for Boost Converter Topolgy

Completed

2013

11

Anjana G.

FPGA Implementation of QFT Based Controller for a Buck Type DC-DC Power Converter

Completed

2012

12

Sarika M

Direct Torque Control of Induction Motor Using Fuzzy Logic

Completed

2012

Research Scholars

Sl. No.

Name of the Student(s)

Topic

Status – Ongoing/Completed

Year of Completion

1

K. Vishnu Raj

Multi Functional Fiber Optic Sensor Based Robotic Arm (Tentative)

Ongoing

 

2.

Ranjitha R.

Reduction of Losses in Microgrid by IoT based Optimization Techniques(Tentative)

Ongoing