Qualification: 
M.Tech
i_mamtha@blr.amrita.edu

Mamatha I. currently serves as Assistant Professor(Sr.Gr) at department of Electrical & Electronics, Amrita School of Engineering, Banglore campus. Currently she is pursuing Ph.D in the area of Architectures for Signal Processing Applications.

Education

YEAR DEGREE/PROGRAM INSTITUTION
2010 M.Tech (VLSI Design) Amrita Vishwa Vidyapeetham, India
1999 B.E(EEE) Mangalore University, India

Publications

Publication Type: Conference Paper

Year of Publication Publication Type Title

2016

Conference Paper

T. Rohith, Samhitha, V. S., and Mamatha, I., “Wireless Transmission of Solar Power using Inductive Resonant Principle”, in 2016 - Biennial International Conference on Power and Energy Systems: Towards Sustainable Energy, PESTSE 2016, 2016.[Abstract]


In this paper, wireleb transmibion of electric power using inductive resonating principle is proposed. Power from solar PV is considered as the source of supply. Comparison of the inductive resonance principle and inductive coupling principle of wireleb power transmibion is carried out. It is observed that efficient transmibion of power at lower frequencies can be achieved using resonance principle with high Q factor transceiver coils. The complete system is designed and implemented on the hardware developed. Input to the circuit is 30V, 0.12A from solar PV and a load of 5V,500mA cell phone is charged by the circuit developed. Overall power efficiency of 69.4% is achieved practically for the wireleb power transmibion using the proposed design at a transmibion frequency of 241kHz and at a distance of 8cm. The transmibion efficiency was found to be approximately 100% at the above mentioned frequency and distance.

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2016

Conference Paper

I. Mamatha, Dr. Shikha Tripathi, and TSB, S., “Pipelined architecture for filter bank based 1-D DWT”, in 2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN), 2016.[Abstract]


A Convolution based parallel and pipelined architecture using MAC Loop Based Filter (MLBF) is proposed in this work. The proposed modification to the MLBF structure produces one output sample for every clock cycle as compared to the MLBF structure which produces two outputs for every four clock cycles. This results in a speed up of 2× which is significant for processing real time signals of long length. Compared to the existing MLBF based 1-D DWT architecture, proposed design uses additional 8 multipliers and 8 adders. The proposed structure is independent of the input size and filter length and performs better than other architectures with same or less area utilization. Generality, scalability, high efficiency of hardware utilization are the other merits of the proposed structure. The architecture is synthesized on Virtex 6 xc6vcx240t-2ff784 FPGA board and can operate at a maximum frequency of 633.43 MHz. The frequency of operation is twice as that of the existing approach. More »»

2016

Conference Paper

K. Gopinathan and Mamatha, I., “Average current mode controlled DC-DC converter using digital controllers”, in Power and Energy Systems: Towards Sustainable Energy (PESTSE), 2016 Biennial International Conference on, 2016.

2016

Conference Paper

V. Chandran, Mamatha, I., and Dr. Shikha Tripathi, “NEDA Based Hybrid Architecture for DCT—HWT”, in VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016 International Conference on, 2016.

2015

Conference Paper

I. Mamatha, Raj, J. N., Dr. Shikha Tripathi, and Dr. T.S.B. Sudarshan, “Systolic architecture implementation of 1D DFT and 1D DCT”, in 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015, 2015.[Abstract]


Discrete Fourier Transform is widely used in signal processing for spectral analysis, filtering, image enhancement, OFDM etc. Cyclic convolution based approach is one of the techniques used for computing DFT. Using this approach an N point DFT can be computed using four pairs of [(M-1)/2]-point cyclic convolution where M is an odd number and N=4M. This work proposes an architecture for convolution based DFT and its FPGA implementation. Proposed architecture comprises of a pre-processing element, systolic array and a post processing stage. Processing element of systolic array uses a tag bit to decide on the type of operation (addition/subtraction) on the input signals. Proposed architecture is simulated for 28 point DFT using ModelSim 6.5 and synthesized using Xilinx ISE10.1 using Vertex 5 xc5vfx100t-3ff1738 FPGA as the target device and can operate at a maximum frequency of 224.9MHz. The performance analysis is carried out in terms of hardware utilization and computation time and compared with existing similar architectures. Further, as the convolution based DCT has two systolic arrays similar to that of DFT, a unified architecture is proposed for 1D DFT/1D DCT. © 2015 IEEE.

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2015

Conference Paper

S. V. B. Bala Sai, Mamatha, I., Dr. Shikha Tripathi, and Sudarshan, T. S. B., “Modified MLBF based architecture for 1-D DWT”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai,India, 2015.[Abstract]


This work proposes an architecture for fast computation of 1-D Discrete Wavelet Transform (DWT). Existing MAC loop based filter (MLBF) is modified and a poly-phase structure for 1-D DWT is proposed. Proposed structure improves the throughput by 1.5x while using almost double the hardware as that of the existing structure. 1-D DWT using existing MLBF structure and proposed structure are simulated using ModelSim and synthesized using Xilinx ISE 14.2 on Virtex-6 XC6VCX240T-2FF784 target device. It is observed that the proposed architecture can be operated at a maximum frequency of 163.59MHz. The simulation results obtained from ModelSim is compared with MatLab R2010a output and found to be accurate. More »»

2015

Conference Paper

K. Gopinathan and Mamatha, I., “Pre-regulated Push Pull Converter for Hybrid Energy Systems”, in Advancements in Power and Energy (TAP Energy), 2015 International Conference on, 2015.

2013

Conference Paper

I. Mamatha, J Raj, N., Dr. Shikha Tripathi, and Sudarshan, T. S. B., “Reduced Complexity Architecture for Convolution Based Discrete Cosine Transform”, in Electronic System Design (ISED), 2013 International Symposium on, 2013.[Abstract]


Discrete Cosine Transform is a popular transform used in signal/image processing applications. Reduction in complexity of hardware architecture for the computation of DCT using the convolution based algorithm is proposed. An N point DCT can be computed through 2 pair of [(M-1)/2] point cyclic convolutions where M is an odd number such that N=2M. The proposed architecture uses only a pair of systolic array where inputs are pipelined against the one in literature where 2 pairs of systolic arrays are used. One of the systolic arrays uses processing element with tag bit and the other one does not need a tag bit. The architecture uses 50% less number of processing elements with just an additional increase in computation time by one unit. The architecture is divided into three stages as preprocessor stage, compute stage where a systolic array computes the cyclic convolution and a post processing stage to process the output of the systolic array to get the actual DCT output. It is observed that the proposed architecture has a reduction of about 42%adders and 64% multipliers as compared to the one in literature. Further, the architecture is simulated in ModelSim 6.5 and synthesized using Xilinx ISE10.1using Vertex 5 FPGA as the target device. The simulation results are matched favourably with that of the output obtained by MATLAB R2010a with MSE of1.3861x10-4.

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Publication Type: Journal Article

Year of Publication Publication Type Title

2015

Journal Article

I. Mamatha, Dr. T.S.B. Sudarshan, Dr. Shikha Tripathi, and Bhattar, N., “Triple-Matrix Product-Based 2D Systolic Implementation of Discrete Fourier Transform”, Circuits, Systems, and Signal Processing, vol. 34, pp. 3221–3239, 2015.[Abstract]


Realization of N -point discrete Fourier transform (DFT) using one-dimensional or two-dimensional systolic array structures has been developed for power of two DFT sizes. DFT algorithm, which can be represented as a triple-matrix product, can be realized by decomposing N into smaller lengths. Triple-matrix product form of representation enables to map the N -point DFT on a 2D systolic array. In this work, an algorithm is developed and is mapped to a two-dimensional systolic structure where DFT size can be non-power of two. The proposed work gives flexibility to choose N for an application where N is a composite number. The total time required to compute N -point DFT is 2 ( N 1 - 1 ) + N 2 + N for any N = N 1 N 2 . The array can be used for matrix–matrix multiplication and also to compute the diagonal elements of triple-matrix multiplication for other applications. The proposed architecture produces in-order stream of DFT sequence at the output avoiding need for reordering buffer. Large sized DFT can be computed by repeatedly using the proposed systolic array architecture. More »»

2012

Journal Article

Dr. K. Deepa, ,, Mamatha, I., and kumar, D. M. Vijaya, “Digital Simulation of SISO-ZVS-Push pull Quasi Resonant Converter for Different Loads”, International Journal of Engineering Research and Applications (IJERA), vol. 2, no. 4, pp. 896–901, 2012.

Publication Type: Book Chapter

Year of Publication Publication Type Title

2014

Book Chapter

I. Mamatha, Dr. Shikha Tripathi, Sudarshan, T. S. B., and Bhattar, N., “Systolic Array Implementation of DFT with Reduced Multipliers Using Triple Matrix Product”, in Advances in Signal Processing and Intelligent Recognition Systems, Springer, 2014, pp. 311–322.[Abstract]


A generic 2D systolic array for N point Discrete Fourier Transform using triple matrix product algorithm is proposed. The array can be used for a non power of two sized N point DFT where N=N1N2 is a composite number. It uses an array of size N2×(N1+1) which requires(2N+4N2) multipliers. For a DFT of size 4N2 (i.e multiple of four), an optimized design which requires 4N2number of multipliers is proposed. It is observed that the proposed optimized structure reduces the number of multipliers by 66.6% as compared to the generic array structure while maintaining the same time complexity. Two examples are illustrated, one with non power of two size DFT and another with a DFT of size 4N2. Both the generic and optimized structures use the triple matrix product representation of DFT. The two structures are synthesized using Xilinx ISE 11.1 using the target device as xc5vtx240t-2ff1759 Virtex-5 FPGA. The proposed structure produces unscrambled stream of DFT sequence at output avoiding a necessity of reordering buffer. The array can be used for matrix -matrix multiplication and to compute the diagonal elements of a triple-matrix multiplication.

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