Publication Type : Conference Proceedings
Publisher : 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015
Source : 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015, Institute of Electrical and Electronics Engineers Inc. (2015)
Url : http://www.scopus.com/inward/record.url?eid=2-s2.0-84937108228&partnerID=40&md5=f98f08c453ddb62b0407c25a432f6aaf
ISBN : 9781479918232
Keywords : Computer architecture, Convolution, Cyclic convolutions, Discrete cosine transforms, Discrete Fourier transforms, Field programmable gate arrays (FPGA), Food products, FPGA implementations, Hardware utilization, Information science, Orthogonal frequency division multiplexing, Performance analysis, Post-processing stages, Proposed architectures, Signal processing, Spectrum Analysis, Systolic architecture, Systolic arrays, Unified architecture
Campus : Bengaluru
School : School of Engineering
Department : Electrical and Electronics
Year : 2015
Abstract : Discrete Fourier Transform is widely used in signal processing for spectral analysis, filtering, image enhancement, OFDM etc. Cyclic convolution based approach is one of the techniques used for computing DFT. Using this approach an N point DFT can be computed using four pairs of [(M-1)/2]-point cyclic convolution where M is an odd number and N=4M. This work proposes an architecture for convolution based DFT and its FPGA implementation. Proposed architecture comprises of a pre-processing element, systolic array and a post processing stage. Processing element of systolic array uses a tag bit to decide on the type of operation (addition/subtraction) on the input signals. Proposed architecture is simulated for 28 point DFT using ModelSim 6.5 and synthesized using Xilinx ISE10.1 using Vertex 5 xc5vfx100t-3ff1738 FPGA as the target device and can operate at a maximum frequency of 224.9MHz. The performance analysis is carried out in terms of hardware utilization and computation time and compared with existing similar architectures. Further, as the convolution based DCT has two systolic arrays similar to that of DFT, a unified architecture is proposed for 1D DFT/1D DCT. © 2015 IEEE.
Cite this Research Publication : I. Mamatha, Raj, J. N., Dr. Shikha Tripathi, and Dr. T.S.B. Sudarshan, “Systolic architecture implementation of 1D DFT and 1D DCT”, in 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015, 2015.