High level objective: Develop next generation VLSI/ SoCs and Testbeds
Leverage Amrita Vishwa Vidyapeetham’s expertise on Wireless Network, Cyber Security and Analog Design
Utilize University of Tokyo’s expertise on Algorithms and Programmable hardware
Build a low cost, PC based, robust testbed to test embedded software running on Design Under Test (typically a micro-controller) using a hybrid approach, combining both event driven and Time triggering mechanisms to satisfy both timeliness and schedulability properties of a terstbed.
To use PMEs techniques (Patterns for Migration of Embedded Systems) to migrate the design of an Insulin Pump prototype from a complex, error prone, event driven architecture to simpler time triggered architure, that has been deterministic experience.
Joint Publication, “MAESTRO: A Time-Driven Embedded Testbed Architecture with Event-Driven 3 Synchronization” co-authored by Sriram Karunagaran (PhD Student, Amrita) and Dr. Fujita at RTAS (IEEE Real Time Technology and Applications Symposium premier conference in the area of Embedded Systems
FDP by Dr. Fujita to Engineering School Faculty, August 2014
Distinguished Lecture by Dr. Fujita to VLSI Students and Faculty, August 2014