Publication Type : Conference Paper
Publisher : 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE
Source : 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE, Bhopal, India, p.224–228 (2017)
Url : https://ieeexplore.ieee.org/abstract/document/8293935
Keywords : Central Processing Unit, Clock gating, Clocks, CMOS circuits, CMOS logic circuits, CPU, current profile, day high performance CPU, Dynamic power dissipation, gated architectures, gating logic, ground bound noise, integrated circuit noise, Integrated circuits, integrated CPU chip, LECTOR, linear current ramp, Logic gates, logic transition, low-power electronics, Microprocessor chips, modern clock gating, noise immune capability, operating clock switching activity, Power lines, Power supplies, power supply circuits, Power Supply Noise, power supply noise reduction, Process Technologies, PSN, simultaneous switching noise, static power dissipation, Switches, Threshold voltage
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Computer Science
Year : 2017
Abstract : With the continuous advent of CMOS, process technologies is extending threat to the noise immune capability of CMOS circuits and the power consumed by them. In present day scenario, though there are a lot of techniques that exist for power reduction, the study of power-supply noise (PSN) based on those techniques is almost unattended in literature. Modern clock gating is one of the best techniques to reduce dynamic and static power dissipation by curbing down the switching activity of the operating clock as well as blocking the direct path between the power lines during logic transition. Therefore, in this paper, we have incorporated gating logic to offer solution to PSN occurrence in CMOS circuits by controlling di/dt, which is generated by the linear current ramp of present day high performance CPU. It is witnessed that, the gated architectures generate very less di/dt with respect to their non-gated counterpart, resulting a noted amount of reduction in PSN.
Cite this Research Publication : Alak Majumder and Dr. Pritam Bhattacharjee, “Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip”, in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), Bhopal, India, 2017, pp. 224–228.