Publication Type : Conference Paper
Publisher : 2017 IEEE International Conference on Circuits and Systems (ICCS)
Source : 2017 IEEE International Conference on Circuits and Systems (ICCS), IEEE, Thiruvananthapuram, India (2017)
Url : https://ieeexplore.ieee.org/abstract/document/8325977
Campus : Amritapuri
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Year : 2017
Abstract : The FFT processor is an essential part utilized for implementing the frameworks of OFDM. Due to its computational necessities, it involves large area and devours high power if implemented in hardware. In this paper, a low power and area efficient pipelined FFT processor using higher radix architecture and folding transformation is presented. The implemented low power FFT has a simple structure as that of radix 2 while utilizing the advantages of higher radix architecture. Higher radix algorithm minimizes the number of multiplication with twiddle factor which in turn reduces the large power utilization in FFT. Radix 22 multipath feedforward architecture is proposed in this paper. As various sequence are computed parallel, a high throughput can be achieved. Hardware resources needed for the presented architecture is much less than the multipath feedback architecture. Reduced chip area and lower power consumption are the merits of this FFT processor. Verilog coding for designed architecture is simulated and synthesized in Xilinx ISE Design Suite 12.1.
Cite this Research Publication : Jiya A. Sam and Aswathy K. Nair, “Fast computation of FFT in OFDM system”, in 2017 IEEE International Conference on Circuits and Systems (ICCS), Thiruvananthapuram, India, 2017.