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Publication Type : Journal Article
Publisher : 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI)
Campus : Coimbatore
School : School of Engineering
Department : Electrical and Electronics
Year : 2021
Abstract : VLSI experiences a key position in many of the signal processing applications. Multiply and Accumulation process is one among the mostly used operation. Power, area and speed are the metrics used to determine the efficiency of a MAC unit. For certain cases each of these metrics plays a key role. In some cases, speed is only concentrated, so the other parameters are not given much priority in that case. This work focuses on two metrics. The power and area is concentrated for the better efficiency in this work. Through the deep analysis of adders, Ripple Carry Adder has shown less area and power consumption than other adders. The processes that are involved in MAC are multiplication, addition and accumulation. The addition of Vedic techniques in a MAC is always an added advantage. So, this work includes development of a 32-bit multiply and accumulate unit using Vedic sutra (Urdhva Tiryakbhyam sutra), accumulation unit involving ripple carry adder (RCA) and its implementation in a 4-tap FIR filter. The results show an efficiency of 5% in area improvement and 9% in power.
Cite this Research Publication : D. S. Manikanta, K. S. S. Ramakrishna, M. Giridhar, N. Avinash, T. Srujan and R. S. R, "Hardware Realization of Low power and Area Efficient Vedic MAC in DSP Filters," 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 46-50, doi: 10.1109/ICOEI51242.2021.9453041.