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Power aware reconfigurable multiprocessor for elliptic curve cryptography

Publication Type : Conference Paper

Publisher : Design, Automation and Test in Europe, 2008. DATE'08

Source : Design, Automation and Test in Europe, 2008. DATE'08, IEEE, Munich (2008)

Url :

ISBN : 9783981080131

Accession Number : 10278157

Keywords : Acceleration, Computer applications, Computer architecture, Concurrent computing, Elliptic curve cryptography, Energy efficiency, Galois fields, Parallel processing, Reconfigurable architectures, Timing

Campus : Bengaluru

School : School of Engineering

Department : Computer Science

Year : 2008

Abstract : Reconfigurable architectures are being increasingly used for their flexibility and extensive parallelism to achieve accelerations for computationally intensive applications. Although these architectures provide easy adaptability, it is so with an overhead in terms of area, power and timing, as compared to non-reconfigurable ASICs. Here, we propose a low overhead reconfigurable multiprocessor, which provides both parallelism and flexibility. The architecture has been evaluated for its energy efficiency for a computational intensive algorithm used in elliptic curve cryptography (ECC). Typically, algorithms in ECC exhibit task-level parallelism and demand large amount of computational resources for custom implementations to achieve a significant speedup. A finite field multiplication in GF(2233) was chosen as a sample application to evaluate the performance on the QuadroCore reconfigurable multiprocessor architecture. A three-fold performance improvement as compared to a single processor implementation was observed. Further, via reconfiguration to suit the application, power savings of about 24% were noted in UMC's 90 nm standard cell technology.

Cite this Research Publication : Dr. Madhura Purnaprajna, Puttmann, C., and Porrmann, M., “Power aware reconfigurable multiprocessor for elliptic curve cryptography”, in Design, Automation and Test in Europe, 2008. DATE'08, Munich, 2008.

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