Faculty Bio

Year : 2021

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA and GPU Architectures

Publisher : IEEE Communications Surveys & Tutorials

Year : 2020

Low cost flex powered gesture detection system and its applications

Cite this Research Publication : P. Telluri, Manam, S., Somarouthu, S., Jayasree M. Oli, and Dr. Ramesh Chinthala, “Low cost flex powered gesture detection system and its applications”, in 2020 Second International Conference on Inventive Research in Computing Applications (ICIRCA), Coimbatore, India, 2020.

Publisher : 2020 Second International Conference on Inventive Research in Computing Applications (ICIRCA)

Year : 2020

High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF(4)

Cite this Research Publication : C. Chandan Kumar and Dr. Ramesh Chinthala, “High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF(4)”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.

Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2020

An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique

Cite this Research Publication : N. Soni and Dr. Ramesh Chinthala, “An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, India, 2020.

Publisher : 2020 International Conference on Smart Electronics and Communication (ICOSEC)

Year : 2019

Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs

Cite this Research Publication : Aswini, Dr. Ramesh Chinthala, and Murty, N. S., “Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs”, in 2019 International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, India, 2019.

Publisher : 2019 International Conference on Computer Communication and Informatics (ICCCI)

Year : 2019

mplementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization

Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2019

Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization

Cite this Research Publication : G. Purushotha Kumar and Dr. Ramesh Chinthala, “Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.

Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)