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Dr. Chinthala Ramesh

Assistant Professor (Sr. Gd.), Electronics and Communication Engineering, School of Engineering, Bengaluru

Qualification: Ph.D
c_ramesh@blr.amrita.edu
Google Scholar Profile
Research Interest: 3D IC based High Performance Computing for Big-data, FPGA based Accelerators, High Performance Computing Architectures, Machine Learning

Bio Publications Professional Appointments Research & Management Experience Major Research Interests Membership in Professional Bodies Certificates, Awards & Recognitions Research Grants Received Keynote Addresses/Invited Talks/Panel Memberships Courses Taught Student Guidance
Bio

Dr. Ramesh Chinthala currently serves as an Assistant Professor (Sr. Gd.) at the Department of Electronics & Communication Engineering, School of Engineering, Bengaluru.

Education

  • Ph.D. in VLSI Domain (2018)
    From: Indian Institute of Science (IISc), Bengaluru
  • M. Tech in VLSI (2010)
    From: Indian Institute of Technology (IIT), Guwahati
  • B. Tech in Electronics & Communication Engineering (2006)
    From: Gokaraju Rangaraju Institute of Engineering and Technology (G.R.I.E.T), affiliated to JNTU University.
Publications

Conference Paper

Year : 2023

Cost Efficient Location Tracking and Health Monitoring System for Soldier Safety

Cite this Research Publication : Raghu J. Mandya,Garugu Sai Kiran Reddy,Chinthala Ramesh, et. al. “Cost Efficient Location Tracking and Health Monitoring System for Soldier Safety”, IEEE 2023 Global Conference on Information Technologies and Communications(GCITC)
Note: Accepted and yet to be published.

Publisher : IEEE

Year : 2021

Complex Binary Number System-based Co-Processor Design for Signal Processing Applications

Cite this Research Publication : Santosh, Sudia Sai, Tandyala Sai Swaroop, Tangudu Kavya, and Ramesh Chinthala. "Complex Binary Number System-based Co-Processor Design for Signal Processing Applications." In 2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), pp. 1-6. IEEE, 2021

Publisher : IEEE

Year : 2020

High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF (4)

Cite this Research Publication : Kumar, Chittibhotla Chandan, and Ramesh Chinthala. "High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF (4)." 2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech). IEEE, 2020.

Publisher : IEEE

Year : 2020

Low cost flex powered gesture detection system and its applications

Cite this Research Publication : P. Telluri, Manam, S., Somarouthu, S., Jayasree M. Oli, and Dr. Ramesh Chinthala, “Low cost flex powered gesture detection system and its applications”, in 2020 Second International Conference on Inventive Research in Computing Applications (ICIRCA), Coimbatore, India, 2020.

Publisher : 2020 Second International Conference on Inventive Research in Computing Applications (ICIRCA)

Year : 2020

High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF(4)

Cite this Research Publication : C. Chandan Kumar and Dr. Ramesh Chinthala, “High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF(4)”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.

Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2020

An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique

Cite this Research Publication : N. Soni and Dr. Ramesh Chinthala, “An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, India, 2020.

Publisher : 2020 International Conference on Smart Electronics and Communication (ICOSEC)

Year : 2019

Area Efficient Architecture for high speed wide data addersin Xilinx FPGAs

Cite this Research Publication : Aswini, Ramesh Chinthala, and N. S. Murty. ``Area Efficient Architecture for high speed wide data addersin Xilinx FPGAs." 2019 International Conference on Computer Communication and Informatics (ICCCI).IEEE, 2019.

Publisher : IEEE

Year : 2019

Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization

Cite this Research Publication : G. Purushotha Kumar and Dr. Ramesh Chinthala, “Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization”, in 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2019.

Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2019

mplementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization

Cite this Research Publication :

Publisher : 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)

Year : 2019

Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs

Cite this Research Publication : Aswini, Dr. Ramesh Chinthala, and Murty, N. S., “Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs”, in 2019 International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, India, 2019.

Publisher : 2019 International Conference on Computer Communication and Informatics (ICCCI)

Journal Article

Year : 2023

An efficient design methodology to speed up the FPGA implementation of artificial neural networks

Cite this Research Publication : Vineetha, K. V., M. Mohit SK Reddy, Chinthala Ramesh, and Dhanesh G. Kurup. "An efficient design methodology to speed up the FPGA implementation of artificial neural networks." Engineering Science and Technology, an International Journal 47 (2023): 101542.
Impact factor: 5.7

Publisher : Engineering Science and Technology, an International Journa

Year : 2022

FPGA Implementation of UaL Decomposition, an alternative to the LU factorization

Cite this Research Publication : Ruchitha, Sai, and Ramesh Chinthala. "FPGA Implementation of UaL Decomposition, an alternative to the LU factorization." Mathematical Statistician and Engineering Applications 71, no. 4 (2022): 1081-1094.

Publisher : Mathematical Statistician and Engineering Applications

Year : 2021

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA and GPU Architectures

Cite this Research Publication : O. Ferraz et al., "A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures," in IEEE Communications Surveys & Tutorials, vol. 24, no. 1, pp. 524-556, Firstquarter 2022, doi: 10.1109/COMST.2021.3126127.

Publisher : IEEE Communications Surveys & Tutorials

Professional Appointments
Year Affiliation
2018 Amrita School of Engineering, Amrita Vishwa Vidyapeetham, deemed to be University
Research & Management Experience

Research Experience

  • Behavioural Modelling and Digital Predistortion (DPD) of RF Power Amplifiers: This is an on-going project funded by ISRO Dr. Dhanesh G. Kurup is Principal Investigator (PI), Dr. R. V. Sanjika Devi is Co-PI, Dr. Chinthala Ramesh is Co-PI. It is for a duration of three-year, started from Jan-2020. A few state-of-the-art DPD algorithms were developed by Dr. Sanjika Devi during her Ph.D. under the guidance of Dr. Danesh G. Kurup. Currently P.G. students are working on the project under my supervision to implement and validate the DPD algorithms on FPGA platform.

Completed and ongoing sub-projects of this research work are:

  • Interfacing of ADC with FPGA is implementedfor converting a continuous time signal to discrete signal (Completed)
  • FPGA implementation of Neural Network based DPD algorithm is completed, verification and a manuscript are under progress based on this work. (On-going)
  • FPGA implementation of Polynomial based DPD algorithm is completed, design verification and a manuscript are under progress based on this work. (On-going)
  • Hardware-Software Co-design of Artificial Neural Network (ANN) Architectures: This is an ongoing Ph. D. research work, carried out by Vineetha Jain, under the Guidance of Dr. Dhanesh G. Kurup. This consists development of both software and hardware. Dr. Dhanesh and Vineetha has developed C++ code for developing the software part of the neural network of interest that implements a function, for example a linear function or a non-linear, and I am guidingfurther to realise the hardware implementation of Artificial Neural Network (ANN) on FPGA, so that the processing time can be improved to achieve ANN based real-time applications.  Currently a manuscript is submitted to a journal, and it is under review.
  • Hardware Library for Machine Learning based reconfigurable digital signal processing units:This is an on-going Ph.D. work, carried out by Swaminadhan Rajula, an assistant professor at ECEdepartment, Amrita School of Engineering who is doing currently part-time Ph. D. under my supervision.
  • Data-level and Task-level parallelism-based system performance optimization: Vani Sree is a Ph.D student and currently working on “Data-level and Task-level parallelism-based system performance optimization” under my supervision.

Management Experience

Current Roles:

  1. School Level Criteria 2 Coordinator (AIQC) for 2023 onwards
  2. Department Level Project Coordinator for B.Tech ECE, EIE and EAC from AY2020-2021 onwards
  3. Syllabus Revision Team Lead for Minors in Embedded System Vertical.
  4. Student Counsellor for 4th ECE B.Tech A2 batch

Previous Roles:I have an opportunity to serve as a faculty advisor, student counsellor, and coordinator, and organizer of various committees, and workshops.

  1. Criteria 4 Coordinator for NBAduring AY2021-22(served successfully)
  2. Criteria File In-charge for P5 Average Grade point file of NBAduring AY2021-22
  3. Publication Committee Memberin VLAI SATA2022, IEEE 3rd International Conference on VLSI Systems, Architecture, Technology, and Applications(VLSI SATA), 15-17December 2022
  4. Faculty Advisor for B.Tech ECE 2018 register batch (served successfully from August 2018 to July 2022)
  5. Student Counsellor for one batch for four years (2018 batch students from August 2018-July 2022)
  6. Tech Program Coordinator for one semester (Academic year 2020-21, Even Sem)
  7. Chethana Club Mentor for one year (Academic year 2020-21)
  8. Faculty in-charge of Files for the following files of NAAC 2019-2020 Assessment
    1. 1 Curriculum Design and Development
    2. 2 Academic Flexibility
    3. 3 Feedback System
  9. Coordinator of “National Workshop on Analog and Mixed Signal IC Design using Mentor Tanner AMS Tool Suite,”conducted on 8th November 2019
  10. Organizerof “A two-days hands workshop on FPGA,” 27th– 28th June 2019
  11. Organizerof “an Inter-Departmental FDP Program on Introduction to Latex,” 2019, Amrita School of Engineering, Bangalore, India.
Major Research Interests
  • VLSI architecture implementations for accelerating various algorithms (Decoding Algorithms:Non-binary LDPC, Turbo decoding algorithms, etc., LU decomposition algorithms)
  • FPGA based High Performance Computing VLSI Architectures (Neural Network Architectures for various applications such as Digital Pre-Distortion (DPD), AM demodulator, Brain Tumor Detector) 
  • Hardware Software Co-design Accelerators for Sparse BLAS Sub-routines on FPGA
Membership in Professional Bodies
  • IEEE Member (Membership number: 97745743)
  • Member in IEEE Circuits and Systems Society, Bangalore
  • Member in IEEE Computer Society, Bangalore
  • Ramesh Chinthala – Google Scholar
Certificates, Awards & Recognitions
  • Publication Committee Memberin VLAI SATA2022,IEEE 3rd International Conference on VLSI Systems, Architecture, Technology, and Applications(VLSI SATA), 15-17December 2022
  • Session Internal Chair in VLSI SATA2022,IEEE 3rd International Conference on VLSI Systems, Architecture, Technology, and Applications(VLSI SATA), 15-17December 2022
  • Session Chair in ICCCI 2019, Session Title: Communication Systems, on 25th Jan 2019
  • Session Chairin UBICNET 2019, 3rd EAI International Conference on Ubiquitous Communication and Network Computing, 8-10 February 2019
  • MHRD Scholarship from July-2010-to-July-2016 while pursuing Ph. D. – IISc Bengaluru
  • GATE Scholarship from July-2008-July-2010 during M. Tech in IIT Guwahati
  • Technical paper reviewer: I was identifiedas prospective reviewerin various prestigious international conferences and invited for reviewing many technical manuscripts in international conferences and served as a reviewer successfully.
    • ICAT 2023, 29thInternational conference on Information, Communication and Automation Technologies, 11th – 14th June 2023, Sarajevo, Bosnia and Herzegovina.
    • VLSI SATA2022,3rdInternational Conference on VLSI Systems, Architecture, Technology, and Applications (VLSI SATA), 15-17 December 2022, Bangalore, India
    • ICITIIT 2022, 3rd International conference on Innovative Trends in Information Technology, 12th – 13th Feb 2022.
    • EAI UBICNET 2021, 4th EAI International Conference on Ubiquitous Communications and Network Computing, March 13th, 2021, Bangalore, India (Online).
    • EAI UBICNET 2019, 2nd EAI International Conference on Ubiquitous Communications and Network Computing,8th – 10th Feb 2019, Bangalore, India.
    • ICIC-2018, 1st International Conference on Intelligent Computing, October 25-27, 2018, Bangalore, India.
Research Grants Received
Year Funding Agency Title of the Project Investigators Status
2020 ISRO Behavioural Modeling and Digital Predistortion (DPD) of RF Power Amplifiers Dr. Dhanesh G. Kurup (PI), Ms. R. V. Sanjika Devi (Co-PI),

Dr. Chinthala Ramesh (Co-PI)

 On-going
Keynote Addresses/Invited Talks/Panel Memberships
  • Doctoral Committee Member of many research scholars (Ph.D. students) from 2019 onwards.
  • Publication Committee Memberin VLAI SATA2022, IEEE 3rd International Conference on VLSI Systems, Architecture, Technology, and Applications(VLSI SATA), 15-17December 2022
  • Session Internal Chair in VLSI SATA2022, IEEE 3rd International Conference on VLSI Systems, Architecture, Technology, and Applications(VLSI SATA), 15-17December 2022
  • Session Chair in ICCCI 2019, Session Title: Communication Systems, on 25th Jan 2019
  • Session Chair in UBICNET 2019, 3rd EAI International Conference on Ubiquitous Communication and Network Computing, 8-10 February 2019
  • Resource person of an Inter-Departmental FDP Program on Introduction to Latex, 2019, Amrita School of Engineering, Bangalore, India.
  • Invited as a Judge for Electronica 2019 a flagship event organized ECIF Club, Amrita School of Engineering, Bangalore, India.
Courses Taught
  • Functional Verification using Hardware Description Languages
  • Design Verification using Hardware Description Languages
  • Introduction Soft Computing
  • Microprocessor and Microcontroller
  • Computer System Architecture
  • Analog Electronic Circuits
  • VLSI Design Laboratory-II
  • Functional Verification Lab
  • Microcontroller Lab
  • Microwave Engineering Lab
  • Signal Processing Laboratory-I
  • Signal Processing Laboratory-II
  • Digital Circuits and Systems Lab
  • Open Lab
  • Electronic Systems Lab
Student Guidance

Undergraduate students

Sl. No. Name of the Student(s) Topic Status – Ongoing/ Completed Year of Completion
1 Ramaraju Padmavathi, Shruthi Repaka, Bhavana FPGA implementation of Convolutional Neural Network based Brain-Tumor Detection Completed 2023
2 Mohammad Sufiyan CAN External Mode Support for STM32 Completed 2023
3 Manda Krishna Sai Digital Certificate Management and Monitoring System Completed 2023
4 Karumuri Naga Sai Srinivasa Sandeep Design of Bus Functional model for the verification of PCIe subsystem Completed 2023
5 Bingumalla Venkata Vinay Kumar, Gokavarapu Sai Akarsh, Naripireddi Hanish Koushik FPGA Implementation of Complex Binary Number System based Divider Completed 2022
6 Charan Chalasani, Pynni Satya Siva Ram, AkkhilSugrivu FPGA Implementation of CBNS multiplier based on CBNS Multiplication Algorithm Completed 2022
7 S Sai Santosh, T Sai Swaroop, Tangudu Kavya Complex Binary Number Systembased AU Design for Signal Processing Applications Completed 2021
8 S Narendra, P Vikranth, P Uday Shankar Teja Memory Sub-systemsfor High-Bandwidth Applications on FPGA Completed 2021
9 D. Meher Vamsi, G. Dinesh, G.Manaswini Implementation of an Area-Power Efficient Digital Power Controller on FPGA Completed 2021
10 S. Sai Manikanta, K. Shashank, S. Shashank A Vlsi Design Of Face Recognition Using Curvelet Transform Completed 2020
11 T.Kaveyarasan, V.Santhosh, V.Deepak Raja Plant Health Analysis Completed 2020
12 Sai Teja Dusanapudi, Vivek Reddy, Palavudi Sravan Smart Controll Mechanism For Bike Security Completed 2020
13 Shruti Kotha, Surya Teja.V, Yeshaswini.N High Performance Nb-Ldpc Decoder Based On Sum Of Product
Algorithm		 Completed 2019
14 Anubhav Kumar Access Control Panel In Mobile Application Through Secured
Communication		 Completed 2019
15 Rishhabh Naik BRIDGEi2i Analytics Solutions Completed 2019

Postgraduate students

Sl. No. Name of the Student(s) Topic Status – Ongoing/ Completed Year of Completion
1 Akshay Bharadwaj Design and implementation of NN based DPD Completed 2023
2 Akanksha Hiremath Design and implementation of Polynomial based DPD Completed 2023
3 Apoorva Design and implementation of Bidirectional LSTM Completed 2023
4 AkshajaKanugovi Design and implementation of Adiabatic Vedic Multiplier using modified RCA Completed 2022
5 Sai Ruchitha FPGA implementation of UaL decomposition, an alternative to the LU Factorization Completed 2021
6 Naveen Soni A Low-Power, Two-Speed, Radix-4, Serial–Parallel Multiplier Completed 2020
7 ChittibhotlaChandan Kumar High Throughput Basic-Set Trellis Min-Max Decoder Architecture Completed 2020
8 HariKrishnan K. Sensor Data Acquisition And Processing Using FPGA Completed 2020
9 Purushotham Kumar Gurrala Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU
Factorization		 Completed 2019

Research scholars

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Mr. Swaminadhan Rajula Hardware library for efficient implementation
of ML (Machine Learning) based Digital Signal
Processing (DSP) hardware units		 Ongoing Ongoing
2 Ms. Kavitha N. Pillai An Efficient Hardware-Software Co-Design
Implementation of Detection and
Classification Algorithms for Cognitive
Radar Architecture		 Ongoing Ongoing
3 Ms. Vanishree K Synergistic Execution in a Heterogeneous
Computing System		 Ongoing Ongoing
4 Nabeel Hashim Advanced Physical Protection System using Deep Learning based Video Analytics Discontinued Ongoing
5 Navya Deepthi Data Acquisition and Signal Processing Accelerators using FPGA for IoT applications Discontinued Ongoing
6 Ms. Vineetha Jain Efficient Real-Time Embedded Approaches for Wireless Systems (Co-Guide) Ongoing Ongoing
7 Ms. Kaveri Hatti Design and Implementation of Optimized PUF Architecture for Hardware Security and Trust (Co-guide) Ongoing Ongoing
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