Faculty Bio

Year : 2020

A novel 8T cell-based subthreshold static RAM for ultra-low power platform applications

Cite this Research Publication : Taehoon Kim, Sivasundar Manisankar and Yeonbae Chung, "A novel 8T cell-based subthreshold static RAM for ultra-low power platform applications", Electronics, Vol. 9, Issue 6, pp. 1-17, 2020.

Publisher : Electronics

Year : 2018

P-channel logic 2 T eDRAM macro with high retention bit architecture

Cite this Research Publication : Sivasundar Manisankar and Yeonbae Chung, "P-channel logic 2 T eDRAM macro with high retention bit architecture", International Journal of Circuit Theory and Applications, Vol. 46, No. 7, pp. 1416-1425, 2018.

Publisher : International Journal of Circuit Theory and Application

Year : 2016

Small-swing cross-coupled inverters based low-power embedded memory in logic CMOS technology

Cite this Research Publication : Sivasundar Manisankar and Yeonbae Chung, "Small-swing cross-coupled inverters based low-power embedded memory in logic CMOS technology", International Journal of Applied Engineering Research, Vol. 11, No. 4, pp. 2749-2754, February 29, 2016

Publisher : International Journal of Applied Engineering Research

Year : 2014

Low Quiescent Current High Performance Capacitor-free LDO Regulator with Optimal Power using CMOS Multi-threshold Transistors

Cite this Research Publication : Sivasundar, M., Krithiga, S., " Low Quiescent Current High Performance Capacitor-free LDO Regulator with Optimal Power using CMOS Multi-threshold Transistors". International Journal
of Scientific and Engineering Research, Vol. 5, No. 4, pp. 757-762, 2014.

Publisher : International Journal of Scientific and Engineering Research

Year : 2015

A Gain Cell eDRAM in Logic CMOS Technology

Publisher : International SoC Design Conference, Gyeongju, South Korea - 2015

Year : 2015

Experimental N-style two-transistor eDRAM in logic CMOS technology

Cite this Research Publication : Hritom Das, Sivasundar Manisankar, Weijie Cheng, and Yeonbae Chung, "Experimental N-style two-transistor eDRAM in logic CMOS technology", 2015 IEEE International Conference on Electron Devices and Solid-State Circuits - 2015, pp. 75-78.

Publisher : 2015 IEEE International Conference on Electron Devices and Solid-State Circuits

Year : 2017

Read disturb-free SRAM bit-cell for subthreshold memory applications

Cite this Research Publication : Hyunmyoung Kim,Taehoon Kim, Sivasundar Manisankar, and Yeonbae Chung, "Read disturb-free SRAM bit-cell for subthreshold memory applications", 2017 IEEE International Conference on Electron Devices and Solid-State Circuits – 2017.

Publisher : 2017 IEEE International Conference on Electron Devices and Solid-State Circuits

Year : 2016

A gain cell array with retention increment design for bit-area efficient on-chip memory applications

Publisher : 2016 International Conference on Solid State Devices and Materials

Year : 2014

Low Quiescent Current High Performance Capacitor-Free LDO Regulator with Optimal Power using CMOS Multi-Threshold Transistor

Cite this Research Publication : Siva Sundar M, “Low Quiescent Current High Performance Capacitor-Free LDO Regulator with Optimal Power using CMOS Multi-Threshold Transistor” International Conference on Trends in Technology for Convergence in AVS Engineering College, Salem in association with University of Oulu,Finalnd - April, 2014

Publisher : International Conference on Trends in Technology for Convergence in AVS Engineering College, Salem in association with University of Oulu