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Publication Type : Conference Paper
Publisher : 2015 IEEE International Conference on Electron Devices and Solid-State Circuits
Source : 2015 IEEE International Conference on Electron Devices and Solid-State Circuits - 2015, pp. 75-78
Url : https://ieeexplore.ieee.org/document/7285053
Campus : Chennai
School : School of Engineering
Center : Amrita Innovation & Research
Department : Electronics and Communication
Verified : Yes
Year : 2015
Abstract : In this work, we demonstrate an experimental eDRAM utilizing logic-compatible N-style 2T gain cell on 130 nm CMOS technology. The memory bit-cell consists of a high-V TH write NMOS and a standard-V TH read NMOS. Combination of a low off-leakage device for write and a high mobility device for read provides much improved retention time and read performance in a compact bit area. The embedded macro operates with 32-kbit density, SRAM-like I/O interface and self-timed 128-row refresh. Measured retention time in typical 32-kbit dies at 1.2 V and room temperature exhibits an average of 2.1 ms.
Cite this Research Publication : Hritom Das, Sivasundar Manisankar, Weijie Cheng, and Yeonbae Chung, "Experimental N-style two-transistor eDRAM in logic CMOS technology", 2015 IEEE International Conference on Electron Devices and Solid-State Circuits - 2015, pp. 75-78.