Publications

Abstract : The main objective of the project is to design an output capacitor-free Low-Dropout Regulator (LDO) using a class-AB operational amplifier and an Assistant Push-Pull Output Stage (APPOS) circuit with multi-threshold transistors. This is done to enable fast-transient response with ultra-low power dissipation. The APPOS circuit will be designed to deliver an extra current that is directly proportional to the output current of the class-AB operational amplifier. This results in the complete separate optimization of the small-signal and large-signal responses of LDO. Thus, without the utilization of area-consuming on-chip capacitors, transient response of LDO can be improved performance wise. The proposed LDO regulator will be designed to use adaptive biasing circuit to provide better transient response compared to the existing LDO regulator. The proposed LDO will be implemented in 90nm CMOS technology with multi threshold devices to improve the slew rate and low power consumption with tradeoff.