Publications

Abstract : This paper describes an innovative low-power embedded memory utilizing small-voltage swing logic CMOS bit-cell. The memory cells are composed of two cross-coupled inverters without any access devices. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method, resulting in low operating power dissipation in the nature. In addition, the design reduces the leakage current in the memory bit-cells during the idle mode. A 16-kbit prototype test chip with the proposed memory techniques has been fabricated in a 180 nm generic CMOS technology, which demonstrated the functionality of the novel embedded memory. Compared to the standard embedded SRAM, the new memory exhibits a 31% reduction in the read power, a 43% reduction in the write power and a nearly 65% reduction in the standby power dissipation, respectively