Publications

Abstract : Abstract This work presents a novel circuit design to improve the data retention of logic-compatible gain cell DRAM. The proposed design utilizes a parasitic capacitance built between the common cell-body and the data storage node. During data write, a voltage toggle on the cell-body couples down the data storage levels. It results in enhancing the data retention in a compact bit-area. The technique also provides much strong immunity from the write disturbance. Measured results at 1.2 V and 85 °C from a 110 nm 64-kbit eDRAM test chip exhibit 63.6 % improved retention time over the conventional design.