Publication Type : Book Chapter
Publisher : Springer Singapore
Source : Lecture Notes in Electrical Engineering
Url : https://doi.org/10.1007/978-981-16-3767-4_48
Campus : Haridwar
School : School of Computing
Year : 2021
Abstract : A 1 KB static random access memory (SRAM) and its control circuit are designed to be implemented in 180 nm technology. Designed SRAM is working on 200 MHz and exhibited good memory cell stability. Overall SRAM architecture was implemented using 6 transistors (6 T) memory cells accessed by row and column decoders. Control logic architecture was also implemented to perform read and write operations using sense amplifier and write driver circuits, respectively. The circuit achieved memory access time of 2.7 ns, which is among the lower values from many earlier published reports for similar technologies, while consuming 5.2 mW power for one byte.
Cite this Research Publication : Abhishek Kumar, Abhishek Sahu, Shree Prakash Tiwari, Design and Performance Evaluation of 1 KB SRAM in SCL 180 nm Technology, Lecture Notes in Electrical Engineering, Springer Singapore, 2021, https://doi.org/10.1007/978-981-16-3767-4_48