Publication Type : Journal Article
Publisher : Elsevier BV
Source : Solid-State Electronics
Url : https://doi.org/10.1016/j.sse.2021.107994
Keywords : Charge plasma (CP), Doping free BJT, Polarity control (PC), TCAD simulation, Logic gates, Virtual doping
Campus : Haridwar
School : School of Computing
Year : 2021
Abstract : Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed using four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) and transient and noise margin analysis are performed. The transient response shows rise and fall time less than 100 ps while worst-case noise margin of 0.25 V observed for an input voltage of 1 V. Moreover, 2:1 multiplexer is also designed and explored for output transient and voltage levels. The delay of less than 2.2 ns is achieved with a nominal deviation of 0.1 V and 0.04 V for high and low output levels respectively.
Cite this Research Publication : Abhishek Sahu, Abhishek Kumar, Shree Prakash Tiwari, Exploration of logic gates and multiplexer using doping-free bipolar junction transistor, Solid-State Electronics, Elsevier BV, 2021, https://doi.org/10.1016/j.sse.2021.107994