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Dr. Yamuna B.

Professor, Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: Ph.D
b_yamuna@cb.amrita.edu
Dr. Yamuna B's Google Scholar Profile
Research Interest: Applications of Error Control Coding, Decoders, Secure Communication Systems, VLSI Architecture for Channel Encoders, VLSI for Communication Systems, Wireless Systems

Bio

Dr. B. Yamuna currently serves as Professor in the Department of Electronics and Communications Engineering at Amrita School of Engineering, Coimbatore. She received the Bachelor of Engineering degree from Bharathiar University, in 1998 and M.E. in VLSI Design from Anna university, in 2004. She obtained her Ph. D. in Error Control Coding in 2013 from Amrita Vishwa Vidyapeetham. She worked as a Lecturer, at PSG College of Technology, Coimbatore, before joining as a faculty at Amrita Vishwa Vidyapeetham in 2000.

Her areas of interest include VLSI for Communication System, Applications of Error Control Coding, Secure Communication System and related areas. She is the Principal Investigator for 3 year (2017-2020) ISRO funded project titled, ‘Reliability based soft decision decoding of Turbo codes for satellite communication’. She has published papers in international journals and international conferences. She has served as Reviewer and Program Committee Member in international conferences.

Publications

Journal Article

Year : 2017

Implementation of turbo code with early iteration termination in GNU radio

Cite this Research Publication : Dr. Salija P. and Dr. Yamuna B., “Implementation of turbo code with early iteration termination in GNU radio”, Journal of Telecommunication, Electronic and Computer Engineering, vol. 9, pp. 53-59, 2017.

Publisher : Journal of Telecommunication, Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka

Year : 2016

Reliability level list-based decoding of multilevel modulated block codes

Cite this Research Publication : Dr. Yamuna B. and T.R, P., “Reliability Level List-Based Decoding of Multilevel Modulated Block Codes”, International Journal of Information and Communication Technology, vol. 9, no. 3, pp. 366-376, 2016.

Publisher : International Journal of Information and Communication Technology.

Year : 2016

Performance Enhanced Iterative Soft-Input Soft-Output Decoding Algorithms for Block Turbo Codes

Cite this Research Publication : V. A. Sudharsan, Karthik, V. B. Vijay, Vaishnavi, J. S. C., Abirami, S. D., and Dr. Yamuna B., “Performance Enhanced Iterative Soft-Input Soft-Output Decoding Algorithms for Block Turbo Codes”, Journal of Telecommunication, Electronic and Computer Engineering, vol. 8, pp. 105-110, 2016.

Publisher : Journal of Telecommunication, Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka,

Year : 2016

Support vector machine based decoding algorithm for BCH codes

Cite this Research Publication : V. Sudharsan and Dr. Yamuna B., “Support vector machine based decoding algorithm for BCH codes”, Journal of Telecommunications and Information Technology, vol. 2016, pp. 108-112, 2016.

Publisher : Journal of Telecommunications and Information Technology, National Institute of Telecommunications.

Year : 2016

An Efficient Early Iteration Termination for Turbo Decoder

Cite this Research Publication : Dr. Salija P. and Dr. Yamuna B., “An Efficient Early Iteration Termination for Turbo Decoder”, Journal of Telecommunications and Information Technology, pp. 113-122 and 112, 2016.

Publisher : Journal of Telecommunications and Information Technology, p.113-122 and 112

Year : 2015

Optimum energy efficient error control techniques in wireless systems: a survey

Cite this Research Publication : Dr. Salija P. and Dr. Yamuna B., “Optimum energy efficient error control techniques in wireless systems: a survey”, Journal of Communications Technology and Electronics, vol. 60, pp. 1257-1263, 2015.

Publisher : Maik Nauka-Interperiodica Publishing

Year : 2015

A Fast Converging Decoding Scheme Based on Particle Swarm Optimization for Block Codes

Publisher : International Journal of Applied Engineering Research

Year : 2014

A Minimal Search Soft Decision List Decoding Algorithm for Reed-Solomon Codes

Cite this Research Publication : Dr. Yamuna B. and Padmanabhan, T. R., “A Minimal Search Soft Decision List Decoding Algorithm for Reed-Solomon Codes”, International Journal of Information and Communication Technology, vol. 6, pp. 71-85, 2014.

Publisher : International Journal of Information and Communication Technology

Year : 2014

Decoding of Linear Block Codes using Partial Reliability Level List based Low Complex A* Algorithm

Cite this Research Publication : , Arjithasindhuri, R., Saiprasanth, L., A. Shakthi, S., Srithar, R., and Dr. Yamuna B., “Decoding of Linear Block Codes using Partial Reliability Level List based Low Complex A* Algorithm”, International Conference on Electrical, Electronics and Computer Engineering, 2014.

Publisher : International Conference on Electrical, Electronics and Computer Engineering

Year : 2013

Reliability level list based direct target codeword identification algorithm for binary BCH codes

Cite this Research Publication : Dr. Yamuna B. and Padmanabhan, T. R., “Reliability level list based direct target codeword identification algorithm for binary BCH codes”, WSEAS Transactions on Communications, vol. 12, pp. 287-299, 2013.

Publisher : WSEAS Transactions on Communications

Year : 2012

A reliability level list based SDD algorithm for binary cyclic block codes

Cite this Research Publication : Dr. Yamuna B. and Padmanabhan, T. R., “A reliability level list based SDD algorithm for binary cyclic block codes”, International Journal of Computers, Communications and Control, vol. 7, pp. 388-395, 2012.

Publisher : International Journal of Computers, Communications and Control

Conference Paper

Year : 2018

Effect of Hardware Trojans on the Performance of a Coded Communication System

Cite this Research Publication : A. R. Aravind, Kesavaraman, S. R., Dr. Karthi Balasubramanian, Dr. Yamuna B., and Lingasubramaniam, K., “Effect of Hardware Trojans on the Performance of a Coded Communication System”, in 2018 IEEE International Conference on Consumer Electronics (ICCE), 2018.

Publisher : IEEE International Conference on Consumer Electronics (ICCE)

Year : 2004

Analog VLSI implementation of Cellular Neural Network and its applications to Image Processing

Cite this Research Publication : S. Veni and Dr. Yamuna B., “Analog VLSI implementation of Cellular Neural Network and its applications to Image Processing”, in International Conference on Systemics, Cybernatics and Informatics, Pentagram Research Centre Pvt Ltd, Hyderabad , 2004.

Publisher : Pentagram Research Centre Pvt Ltd

Conference Proceedings

Year : 2019

Design and Implementation of Interleaver in GNU Radio for short block length Turbo codes

Cite this Research Publication : Sreedevi M., Dr. Yamuna B., and Dr. Salija P., “Design and Implementation of Interleaver in GNU Radio for short block length Turbo codes”, 2019 9th International Conference on Advances in Computing and Communication (ICACC). IEEE, Kochi, India, 2019.

Publisher : ICACC

Year : 2019

Effect of sign-bit-flipping trojan on turbo coded communication systems

Cite this Research Publication : K. Balasubramanian, Dr. Yamuna B., Dr. Salija P., K. Lingasubramanian, and Dr. Deepak Mishra, “Effect of sign-bit-flipping trojan on turbo coded communication systems”, Proceedings of the 20th International Conference on Distributed Computing and Networking. 2019.

Publisher : Proceedings of the 20th International Conference on Distributed Computing and Networking.

Year : 2017

A Low Complex Turbo Decoding Algorithm with Early Iteration Termination

Cite this Research Publication : C. R. Seethal and Dr. Yamuna B., “A Low Complex Turbo Decoding Algorithm with Early Iteration Termination”, 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI). pp. 325-331, 2017.

Publisher : 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

Year : 2005

Hardware implementation of CNN

Cite this Research Publication : S. Veni and Dr. Yamuna B., “Hardware implementation of CNN”, International Conference on Intelligent sensing and information Processing (ICISIP). IEEE , Le Royal Meridian, Chennai, pp. 320-325, 2005.

Publisher : IEEE , Le Royal Meridian, Chennai

Education
  • 2013: Ph. D. in Error Control Coding
    Amrita VishwaVidyapeetham
  • 2004: M. E. in VLSI Design
    Anna University
  • 1998: Bachelor of Engineering
    Bharathiar University
Professional Experience
Year Affiliation
August 2021 – Present Professor, Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham
Domain : Teaching, Research, Funded Projects and Dept Administration
July 2013 – August 2021 Associate Professor, Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham
Domain : Teaching, Research, Funded Projects and Dept Administration
July 1, 2008 Assistant Professor (S.G), Amrita VishwaVidyapeetham
Domain : Teaching, Research and Dept Administration
February 1, 2005 Assistant Professor (Senior Lecturer), Amrita Vishwa Vidyapeetham
Domain : Teaching
June 12, 2000 Lecturer, Amrita Vishwa Vidyapeetham
Domain : Teaching
June 19, 1999 Lecturer, PSG College of Technology
Domain : Teaching
Academic Responsibilities
SNo Position Class / Batch
1. Program Coordinator (June 2016 to till date) PG VLSI Design
2. M.Tech VLSI Design BOS member (2016)
3. Publication Committee (2016-till date M.Tech VLSI Design)
4. Member-PG admission committee (2016 to till date)
5 Publication Committee (2015-2016 B.Tech )
8. PhD admission coordinator (2014)
9. Class Advisor 2012-2016
10. Batch Coordinator 2012-2016
11. Class Advisor 2008-2012
Undergraduate Courses Handled
  1. Digital System Design
  2. Electronics Circuits
  3. Information Theory and Coding Techniques
  4. Spread Spectrum Communication
  5. Communication Engineering
  6. Solid State Circuits
  7. Advanced Digital Design
Post-Graduate / PhD Courses Handled
  1. VLSI Signal Processing (VLSI Design)
  2. Solid State Device modelling and Simulation (VLSI Design)
  3. Information Theory and coding (Cybersecurity)
  4. Estimation and Detection Theory(CESP)
  5. Coding Theory (CESP)
Participation in Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1. COMSNETS 2018 IISc, Bangalore January 7, 2018 Focus on use of Deep learning techniques for communication algorithms.
2. National Workshop on Embedded design flow using Xilinx ZYNQ SoC Dept of ECE, ASE, Coimbatore February 27 – 28, 2015 Domain research focus
3. National Workshop on RF/Wireless System Design Solution from Xilinx Sri Ramakrishna Engineering College October 9 – 10, 2014 Domain research focus
4. One day Research seminar on Emerging perspectives in Nanoelectronics R&D Dept of ECE, ASE, Coimbatore September 19, 2014 Domain research focus
Organizing Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1. National Symposium on Green Electronics DRDO & Honeywell Dec 12&13, 2014 Research focus
Academic Research – PhD Guidance
SNo Name of the Scholar Specialization / Title Duration / Registration Status / Year
1. Ms. Salija P. Error control coding Aug 2014 Post Qualifying exam
2. Ms. Seethal C.R. Error control coding July 2018 Course work
Academic Research – PG Projects
SNo Name of the Scholar Programme Specialization Duration Status
1. Eluri Kalpana VLSI Design Hardware design 2017-18 Completed
2. Aiswarya M. S. VLSI Design Hardware design 2017-18 Completed
3 Durga P. CESP SOVA in GNU radio 2017-18 Completed
4 Nikhila S. VLSI Design FPGA based Design of Turbo decoder 2018-19 Ongoing
5 Sreedevi M. CESP Communication algorithm 2018-19 Ongoing
6 Anupama E. CESP Deep learning for communication 2018-19 Ongoing
Sanctioned Projects
SNo Title Agency Amount Duration Status
1. Reliability based soft decision decoding of Turbo codes for satellite communication ISRO Rs.30.20 Lakhs 3 years Ongoing
Research Laboratories – Developed / Associated
Location Name and Year Sponsoring Agency Domain No. of Publications No. of Funded projects No. of PG / PhDs
D-302, AB-II Information Processing and Coding Lab (2018) ISRO VLSI Signal Processing, Communication 2(Published) 5(Accepted) 1 PG:6 PhD:2
International and National Collaborations
SNo Title Agency Amount Duration Status
1. Security aware realizations of hardware systems Dept of Electrical Engineering, University of Alabama Conference fee payments. Joint Paper publications, Since Oct 2017 Ongoing
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