Qualification: 
Ph.D
b_yamuna@cb.amrita.edu

Dr. B. Yamuna currently serves as Associate Professor in the Department of Electronics and Communications Engineering at Amrita School of Engineering, Coimbatore. She received the Bachelor of Engineering degree from Bharathiar University, in 1998 and M.E. in VLSI Design from Anna university, in 2004. She obtained her Ph. D. in Error Control Coding in 2013 from Amrita Vishwa Vidyapeetham. She worked as a Lecturer, at PSG College of Technology, Coimbatore, before joining as a faculty at Amrita Vishwa Vidyapeetham in 2000.

Her areas of interest include VLSI for Communication System, Applications of Error Control Coding, Secure Communication System and related areas. She is the Principal Investigator for 3 year (2017-2020) ISRO funded project titled, ‘Reliability based soft decision decoding of Turbo codes for satellite communication’. She has published papers in international journals and international conferences. She has served as Reviewer and Program Committee Member in international conferences.

Education

  • 2013: Ph. D. in Error Control Coding
    Amrita VishwaVidyapeetham
  • 2004: M. E. in VLSI Design
    Anna University
  • 1998: Bachelor of Engineering
    Bharathiar University

Professional Experience

Year Affiliation
July 2013 - Present Associate Professor, Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham
Domain : Teaching, Research, Funded Projects and Dept Administration
July 1, 2008 Assistant Professor (S.G), Amrita VishwaVidyapeetham
Domain : Teaching, Research and Dept Administration
February 1, 2005 Assistant Professor (Senior Lecturer), Amrita Vishwa Vidyapeetham
Domain : Teaching
June 12, 2000 Lecturer, Amrita Vishwa Vidyapeetham
Domain : Teaching
June 19, 1999 Lecturer, PSG College of Technology
Domain : Teaching

Academic Responsibilities

SNo Position Class / Batch
1. Program Coordinator (June 2016 to till date) PG VLSI Design
2. M.Tech VLSI Design BOS member (2016)  
3. Publication Committee (2016-till date M.Tech VLSI Design)  
4. Member-PG admission committee (2016 to till date)  
5 Publication Committee (2015-2016 B.Tech )  
8. PhD admission coordinator (2014)  
9. Class Advisor 2012-2016
10. Batch Coordinator 2012-2016
11. Class Advisor 2008-2012

Undergraduate Courses Handled

  1. Digital System Design
  2. Electronics Circuits
  3. Information Theory and Coding Techniques
  4. Spread Spectrum Communication
  5. Communication Engineering
  6. Solid State Circuits
  7. Advanced Digital Design

Post-Graduate / PhD Courses Handled

  1. VLSI Signal Processing (VLSI Design)
  2. Solid State Device modelling and Simulation (VLSI Design)
  3. Information Theory and coding (Cybersecurity)
  4. Estimation and Detection Theory(CESP)
  5. Coding Theory (CESP)

Participation in Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. COMSNETS 2018 IISc, Bangalore January 72018 Focus on use of Deep learning techniques for communication algorithms.
2. National Workshop on Embedded design flow using Xilinx ZYNQ SoC Dept of ECE, ASE, Coimbatore February 27 - 28, 2015 Domain research focus
3. National Workshop on RF/Wireless System Design Solution from Xilinx Sri Ramakrishna Engineering College October 9 - 10, 2014 Domain research focus
4. One day Research seminar on Emerging perspectives in Nanoelectronics R&D Dept of ECE, ASE, Coimbatore September 19, 2014 Domain research focus

Organizing Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. National Symposium on Green Electronics DRDO & Honeywell Dec 12&13, 2014 Research focus

Academic Research – PhD Guidance

SNo Name of the Scholar Specialization / Title Duration / Registration Status / Year
1. Ms. Salija P. Error control coding Aug 2014 Post Qualifying exam
2. Ms. Seethal C.R. Error control coding July 2018 Course work

Academic Research – PG Projects

SNo Name of the Scholar Programme Specialization Duration Status
1. Eluri Kalpana VLSI Design Hardware design 2017-18 Completed
2. Aiswarya M. S. VLSI Design Hardware design 2017-18 Completed
3 Durga P. CESP SOVA in GNU radio 2017-18 Completed
4 Nikhila S. VLSI Design FPGA based Design of Turbo decoder 2018-19 Ongoing
5 Sreedevi M. CESP Communication algorithm 2018-19 Ongoing
6 Anupama E. CESP Deep learning for communication 2018-19 Ongoing

Sanctioned Projects

SNo Title Agency Amount Duration Status
1. Reliability based soft decision decoding of Turbo codes for satellite communication ISRO Rs.30.20 Lakhs 3 years Ongoing

Research Laboratories – Developed / Associated

Location Name and Year Sponsoring Agency Domain No. of Publications No. of Funded projects No. of PG / PhDs
D-302, AB-II Information Processing and Coding Lab (2018) ISRO VLSI Signal Processing, Communication 2(Published) 5(Accepted) 1 PG:6 PhD:2

International and National Collaborations

SNo Title Agency Amount Duration Status
1. Security aware realizations of hardware systems Dept of Electrical Engineering, University of Alabama Conference fee payments. Joint Paper publications, Since Oct 2017 Ongoing

Publications

Publication Type: Conference Paper

Year of Publication Title

2018

A. R. Aravind, Kesavaraman, S. R., Dr. Karthi Balasubramanian, Dr. Yamuna B., and Lingasubramaniam, K., “Effect of Hardware Trojans on the Performance of a Coded Communication System”, in 2018 IEEE International Conference on Consumer Electronics (ICCE), 2018.[Abstract]


Pernicious Trojan circuits inserted during the design or fabrication phases of an integrated circuit may cause undesirable effects in the designed system. In the case of communication systems, incorrect decoding of the received information is an issue that may lead to serious consequences. In this paper, we study the performance degradation of a noisy coded communication system, due to the presence of hardware Trojans in the decoding unit. It can be seen that the Trojans have negligible effect at low SNRs while there is a statistically significant increase in the bit error rate (p <; 0.01) at higher SNRs. At high SNRs, we expect the bit error rate to tend towards zero, but it is observed that even with the Trojan being activated only once during the entire duration of the transmission, there is a constant bit error rate of the order of 10-4.

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2004

S. Veni and Dr. Yamuna B., “Analog VLSI implementation of Cellular Neural Network and its applications to Image Processing”, in International Conference on Systemics, Cybernatics and Informatics, Pentagram Research Centre Pvt Ltd, Hyderabad , 2004.

Publication Type: Conference Proceedings

Year of Publication Title

2017

C. R. Seethal and Dr. Yamuna B., “A Low Complex Turbo Decoding Algorithm with Early Iteration Termination”, 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI). pp. 325-331, 2017.[Abstract]


In this paper a log-MAP turbo decoding algorithm which incorporates reliability threshold based trellis branch elimination together with mean based early iteration termination has been proposed. The proposed algorithm reduces computational complexity by eliminating branches in trellis. Since the minimum Log Likelihood Ratio (LLR) obtained for each iteration varies with channel conditions, an early iteration termination based on the mean of extrinsic information has been combined with branch elimination. Here, complexity mitigation is done both in terms of branch elimination and iteration reduction with negligible performance degradation. By reducing the computational complexity, decoding delay, power consumptions and error accumulation imparted by additional iterations etc can be minimized.

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2005

S. Veni and Dr. Yamuna B., “Hardware implementation of CNN”, International Conference on Intelligent sensing and information Processing (ICISIP). IEEE , Le Royal Meridian, Chennai, pp. 320-325, 2005.[Abstract]


The requisite properties of analog CNN components, like the Gilbert multiplier, Operational transconductance amplifier, and the current mirror, were separately estimated. Interconnect for a single cell was analyzed , and extended for a 3 /spl times/3 CNN, that has been implemented. A programmable integration time-constant and a template programmability is found possible. It is also seen that implementation is possible at very low power levels, typically 124 uW. The network considered in this design is a continuous-time rectangular type CNN with r = 1. In this paper the network was implemented using analog VLSI techniques and their performance was verified using cadence spectre IC5. The designed CNN could be used for the applications such as image processing, solution of partial differential equation, modelling of nonlinear phenomenon, physical system simulation, etc.

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Publication Type: Journal Article

Year of Publication Title

2017

P. Salija and Dr. Yamuna B., “Implementation of turbo code with early iteration termination in GNU radio”, Journal of Telecommunication, Electronic and Computer Engineering, vol. 9, pp. 53-59, 2017.[Abstract]


Wireless communication systems demand energy efficient and performance optimized error correction scheme. Turbo code, an iterative error correction code, shows strong error correction capability. Many wireless communication systems use Turbo code in their standards due to its near ideal performance. The iterative nature of Turbo decoder introduces additional computations, decoding delay, and power consumption. The number of iterations required to obtain the desired output varies with the channel conditions. Early iteration termination at appropriate time reduces the computational complexity without performance degradation. An early iteration termination based on the absolute value of the mean of extrinsic information has been proposed recently. This technique efficiently terminates the iteration at low and high SNR conditions and also minimizes the half iterations. Software Defined Radio (SDR), a communication system technology, is a common platform that supports various standards. GNU Radio is the software part of SDR that allows implementing various features of communication systems. A low complex Turbo decoder in GNU Radio along with Universal Software Radio Peripheral (USRP) helps to implement real time applications with low decoding delay and reduced complexity. In this paper, Turbo CODEC with early iteration termination has been implemented in GNU Radio platform.

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2016

V. A. Sudharsan, Karthik, V. B. Vijay, Vaishnavi, J. S. C., Abirami, S. D., and Dr. Yamuna B., “Performance Enhanced Iterative Soft-Input Soft-Output Decoding Algorithms for Block Turbo Codes”, Journal of Telecommunication, Electronic and Computer Engineering, vol. 8, pp. 105-110, 2016.[Abstract]


Recently, there has been an extensive research on the decoding of Block Turbo Codes (BTCs) achieving near optimum performance at higher noise levels. In this paper, two performances for enhancing novel BTC decoders based on Particle Swarm Optimisation (PSO) and Support Vector Machine (SVM) have been proposed. The decoding latency for the PSO based BTC decoder was much lesser for higher block length BTCs. SVM was adaptable to the channel characteristics and this made it easy to design application specific decoder for BTCs based on SVM.

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2016

Dr. Yamuna B. and T.R, P., “Reliability Level List-Based Decoding of Multilevel Modulated Block Codes”, International Journal of Information and Communication Technology, vol. 9, no. 3, pp. 366-376, 2016.[Abstract]


Different Soft decision decoding approaches for block codes which refine the Hard decision decoding have been reported. These approaches have varying degrees of complexity and performance enhancement. The Reliability Level List (RLL) based decoding scheme for block codes directly uses the reliability of the received bit with corresponding dividend in decoding. With this scheme it has become possible to identify the Target Codeword (TCW) directly obviating the need for forming an intermediate set of candidate codewords and then selecting the decoded codeword from them. This opens up the possibility of exploring a comprehensive generalization of the RLL concept for any block code and any baseband scheme. Such a generalization for block codes with M-QAM signaling scheme is established in the paper.

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2016

P. Salija and Dr. Yamuna B., “An Efficient Early Iteration Termination for Turbo Decoder”, Journal of Telecommunications and Information Technology, pp. 113-122 and 112, 2016.[Abstract]


Turbo code finds wide applications in mobile communication, deep space communication, satellite communication and short-range communication despite its high computational complexity and iterative nature. Realizing capacity approaching turbo code is a great achievement in the field of communication systems due to its efficient error correction capability. The high computational complexity associated with the iterative process of decoding turbo code consumes large power, introducing decoding delay, and reducing the throughput. Hence, efficient iteration control techniques are required to make the turbo code more power efficient. In this paper, a simple and efficient early iteration termination technique is introduced based on absolute value of the mean of extrinsic information at the component decoders of turbo code. The simulation results presented clearly show that the proposed method is capable of reducing the average number of iterations while maintaining performance close to that of fixed iteration termination. The significant reduction in iteration achieved by the method reduces decoding delay and complexity while maintaining Bit Error Rate performance close to standard fixed iteration turbo decoder. Keywords—early termination, complexity reduction, mean of extrinsic information, turbo decoder.

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2016

V. Sudharsan and Dr. Yamuna B., “Support vector machine based decoding algorithm for BCH codes”, Journal of Telecommunications and Information Technology, vol. 2016, pp. 108-112, 2016.[Abstract]


Modern communication systems require robust, adaptable and high performance decoders for efficient data transmission. Support Vector Machine (SVM) is a margin based classification and regression technique. In this paper, decoding of Bose Chaudhuri Hocquenghem codes has been approached as a multi-class classification problem using SVM. In conventional decoding algorithms, the procedure for decoding is usually fixed irrespective of the SNR environment in which the transmission takes place, but SVM being a machine-learning algorithm is adaptable to the communication environment. Since the construction of SVM decoder model uses the training data set, application specific decoders can be designed by choosing the training size efficiently. With the soft margin width in SVM being controlled by an equation, which has been formulated as a quadratic programming problem, there are no local minima issues in SVM and is robust to outliers. © 2016, National Institute of Telecommunications. More »»

2015

Dr. Yamuna B., V. Krishna, S. Vamsi, Kolisetty, H., C. Krishna, V., Raju, R. R., and Reddy, S. B. A., “A Fast Converging Decoding Scheme Based on Particle Swarm Optimization for Block Codes”, International Journal of Applied Engineering Research, vol. 10, no. 13, pp. 33161-33164, 2015.

2015

P. Salija and Dr. Yamuna B., “Optimum energy efficient error control techniques in wireless systems: a survey”, Journal of Communications Technology and Electronics, vol. 60, pp. 1257-1263, 2015.[Abstract]


Energy efficiency and error free transmission have become prime concerns in wireless communication in recent years. Such networks are much more affected by errors due to dynamic channel conditions than normal wired networks. Error control coding is commonly used in the entire range of information com-munication to reduce the harmful effects of the channel. In order to overcome the communication errors in an energy efficient way, an error control mechanism with less complexity is required. Energy efficient error control techniques to prolong network lifetime in resource limited network and wireless communication remains a challenge. This paper forms a survey of recent developments on the various energy efficient error control coding techniques used in wireless communication and resource limited networks/hardware. © 2015, Pleiades Publishing, Inc.

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2014

, Arjithasindhuri, R., Saiprasanth, L., A. Shakthi, S., Srithar, R., and Dr. Yamuna B., “Decoding of Linear Block Codes using Partial Reliability Level List based Low Complex A* Algorithm”, International Conference on Electrical, Electronics and Computer Engineering, 2014.

2014

Dr. Yamuna B. and Padmanabhan, T. R., “A Minimal Search Soft Decision List Decoding Algorithm for Reed-Solomon Codes”, International Journal of Information and Communication Technology, vol. 6, pp. 71-85, 2014.

2013

Dr. Yamuna B. and Padmanabhan, T. R., “Reliability level list based direct target codeword identification algorithm for binary BCH codes”, WSEAS Transactions on Communications, vol. 12, pp. 287-299, 2013.[Abstract]


In BCH coded schemes the reliability information available with the demodulated bits can be effectively used for soft decision decoding (SDD) to improve signal to noise ratio performance. Chase algorithms, their adaptations, and modifications available for SDD trade complexity for performance to different levels. A new iterative algorithm - Reliability Level List based Direct Target Codeword Identification Algorithm (DTCI) - is proposed in the paper; the algorithm yields the best that is possible with SDD. The concept of reliability level list (RLL) introduced in the paper is central to the application of the algorithm. At every stage of the iterative process followed, the algorithm uses the reliability information of the bits and identifies the next most likely candidate word to be examined. This ensures that the correct decoded codeword is identified through the shortest number of steps. Detailed simulation studies with different BCH codes amply bring out the effectiveness and superiority of the algorithm.

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2012

Dr. Yamuna B. and Padmanabhan, T. R., “A reliability level list based SDD algorithm for binary cyclic block codes”, International Journal of Computers, Communications and Control, vol. 7, pp. 388-395, 2012.[Abstract]


Soft decision decoding (SDD) provides a better coding gain by making use of the unquantized channel output. In this paper we introduce the concept of a Reliability Level List (RLL); based on the RLL a new SDD algorithm for Binary Phase Shift Keying (BPSK) based binary cyclic block codes is proposed. The algorithm guarantees to extract the most reliable codeword in an iterative manner. The formation of the RLL involves a search for the next possible entry into the RLL based on the error probability which is a reflection of the reliability values of the bits of the received word obtained from the channel. The procedure for the formation of RLL which is the central idea of the paper is given as a structured algorithm. © 2006-2012 by CCC Publications.

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