Qualification: 
M.Tech
m_navya@cb.amrita.edu
Phone: 
+91 422 2685000 Ext. 5726

Navya Mohan is working as an Assistant Professor in ECE Department at Amrita Vishwa Vidyapeetham, Coimbatore. She completed her M.Tech in VLSI Design from Amrita Vishwa Vidyapeetham in 2013 and B.Tech in Electronics and Communication Engineering from College of Engineering Adoor in 2010. Her area of interests includes Low power VLSI Testing and Reconfigurable Computing. She is also GATE qualified.

Education

  • Pursuing: Ph. D. in VLSI Testing
    Amrita Vishwa Vidyapeetham
  • 2013: M. Tech. in VLSI Design
    Amrita Vishwa Vidyapeetham

Professional Experience

Year Affiliation
2013 - Till Present Assistant Professor, Amrita Vishwa Vidyapeetham
Domain : Teaching and Research

Academic Responsibilities

SNo Position Class / Batch
1. Class Adviser 2016 - 20

Undergraduate Courses Handled

  1. VLSI Design
  2. Electronics Circuits
  3. Linear Integrated Circuits
  4. Digital Circuits and Systems
  5. Microcontroller and its Applications
  6. Computer System Architecture

Post-Graduate / PhD Courses Handled

  1. Introduction to Computer Architecture (Automotive Electronics)

Participation in Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. ISTE Workshop on Signals and Systems IIT Kharagpur 2 – 12 January 2014 Teaching learning process

Academic Research – PG Projects

SNo Name of the Scholar Programme Specialization Duration Status
1. Veena V. VLSI Design Low Power VLSI Testing 2018-19 Ongoing
2. Anthony Thomas VLSI Design Low Power VLSI Testing 2018-19 Ongoing

Developmental Activities

SNo Name & Description Outcome
1. Instruction material for ECE100 Electronics Engineering Course for 2014 Curriculum Uniform course delivery throughout all the branches of Engineering.

Publications

Publication Type: Conference Paper

Year of Publication Title

2017

N. Mohan, Krishnan, M., S. Rai, K., Mathu, M. M., and Sivakalyan, S., “Efficient Test Scheduling for Reusable BIST in 3D stacked ICs”, in 2017 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2017, 2017, vol. 2017-January, pp. 1349-1355.[Abstract]


VLSI testing is essential with advancing technology as it helps improve yield and enables the detection of faulty chips after manufacturing. The factors which play important roles are the power dissipation and time taken during the process of testing. BIST, Built-In Self-Test is a testing technique which enables the device to test itself. A reusable BIST is proposed which allows the usage of the same BIST for pre-bond and post-bond testing. The proposed BIST is used for testing 3D stacked ICs. Test scheduling is a critical problem that is faced while 3D stacked ICs are tested as the same tests which are performed during prebond might need to be performed simultaneously or so during post-bond. Here, we propose a modified Skyline algorithm to obtain an improved test schedule. The algorithm is tested on the inputs from ISCAS-85 benchmark circuits. The obtained results are compared with the results from traditional Skyline algorithm.

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Publication Type: Journal Article

Year of Publication Title

2016

N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.[Abstract]


This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing.

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2014

B. D. Kumar Reddy and Mohan, N., “N-Detect Test Pattern Generation And Relaxation Using ZDD”, International Journal of Electrical, Electronics and Data Communication, vol. 2, no. 7, p. Online-Ressource, 2014.[Abstract]


Manufacturing test is a major challenge for very-deep submicron (VDSM) integrated circuits. Mandated productquality levels must be ensured by screening all defective devices before they are shipped. However, defect screening remains a formidable problem, especially for VDSM process technologies, since it is impossible to explicitly target every possible defect. This paper mainly deals with a method to generate N-detect test sets that provide high defect coverage making judicious use of new pattern quality metrics which is basically depended on the concept of ZDD. Simulation results for benchmark circuits show that, this method provides higher fault coverage and coverage ramp-up compared to other methods using BDD as ZDD provides an efficient way of solving problems expressed in terms of set theory and cube vectors. More »»