Qualification: 
M.Tech
Email: 
m_navya@cb.amrita.edu

Navya Mohan currently serves as Assistant Professor at the department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore. She completed her BTech in Electronics and Communication from College of Engineering, Adoor, CUSAT in the year 2010 and M.Tech in VLSI Design from Amrita Vishwa Vidyapeetham in the year 2013. 

Ongoing projects:

  • Test data compression using EDT
  • Reconfigurable Floating Point Adder/Subtractor

Teaching:

  • VLSI Design
  • VLSI Testing
  • Microprocessor
  • Microcontroller
  • Electronic Circuits

Publications

Publication Type: Journal Article

Year of Publication Publication Type Title

2016

Journal Article

N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.[Abstract]


This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing. © Copyright 2016 Inderscience Enterprises Ltd.

More »»

2014

Journal Article

B. D. Kumar Reddy and Mohan, N., “N-Detect Test Pattern Generation And Relaxation Using ZDD”, International Journal of Electrical, Electronics and Data Communication, vol. 2, no. 7, p. Online-Ressource, 2014.[Abstract]


Manufacturing test is a major challenge for very-deep submicron (VDSM) integrated circuits. Mandated productquality levels must be ensured by screening all defective devices before they are shipped. However, defect screening remains a formidable problem, especially for VDSM process technologies, since it is impossible to explicitly target every possible defect. This paper mainly deals with a method to generate N-detect test sets that provide high defect coverage making judicious use of new pattern quality metrics which is basically depended on the concept of ZDD. Simulation results for benchmark circuits show that, this method provides higher fault coverage and coverage ramp-up compared to other methods using BDD as ZDD provides an efficient way of solving problems expressed in terms of set theory and cube vectors. More »»
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