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12-Bit SAR ADC Design in SCL 180 nm for Sensor Interface Applications

Publication Type : Conference Paper

Publisher : Springer Nature Singapore

Source : Lecture Notes in Electrical Engineering

Url : https://doi.org/10.1007/978-981-99-4495-8_18

Campus : Haridwar

School : School of Computing

Year : 2023

Abstract : A high-resolution analog-to-digital converter (ADC) is presented in this paper for application in sensor signal conditioning circuits. Based on the requirements of low complexity, low speed of operation, and moderate resolution, successive approximation register (SAR) ADC is most suitable. All the sub-circuits, i.e. comparator, sample and hold (with bootstrapped switching technique), SAR logic, and differential charge scaling digital-to-analog converter (DAC) circuits are designed, simulated, and verified using Cadence Virtuoso with SCL 180 nm PDK. The proposed design achieved 1.1 MS/s for 12-bit resolution with SDNR and ENOB of 73.54 dB and 11.92 bits, respectively.

Cite this Research Publication : Abhishek Kumar, Abhishek Sahu, Anurag Dwivedi, Shree Prakash Tiwari, 12-Bit SAR ADC Design in SCL 180 nm for Sensor Interface Applications, Lecture Notes in Electrical Engineering, Springer Nature Singapore, 2023, https://doi.org/10.1007/978-981-99-4495-8_18

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