Publication

Abstract : The performance of integrated circuits in modern technology is influenced by on-chip global communication, essential for data and control transfers between chip modules. A key challenge to high-performance communication is inter-symbol interference (ISI), where pulses spread beyond their time slots, causing interference with neighboring pulses and increasing errors at the receiver. This study presents a mathematical model-based data reconstruction algorithm to mitigate ISI in the continuous-time linear frequency domain for high-speed serial communication. A unit square wave pulse represents logic 1, and after applying the Fourier transform, channel loss, and Inverse Fourier Transform, the signal is introduced and stored at the receiver as a transfer function for logic 1. A proposed algorithm uses this data to estimate transmitted signals. The model is tested at frequencies from 10 to 20 GHz in channels of 10′′, 12.5′′, and 15′′ lengths using an n-pseudorandom binary sequence. Signal-to-noise ratio (SNR) and bit error rate (BER) confirm accuracy of this approach, while trade-off studies of BER-frequency-SNR and BER-channel length-SNR identify optimal channel lengths and frequencies for minimal noise and error recovery. The eye diagram characteristics in the optimal scenario validate the proposed model’s superior performance, demonstrating enhanced signal integrity. A detailed comparative analysis highlights its advantages in BER and eye metrics over existing techniques, confirming its suitability for high-speed on-chip serial communication.