Publications

Abstract : The project focuses on the implementation of an n-tap Biquadratic filter using modified booth multiplier. The proposed multiplier deploys an efficient method to multiply two signed binary numbers in two’s complement. It uses radix- 4 algorithm which reduces the number of partial products which improves the speed of the booth multiplier. An effective algorithm where the multiplier consumes very less power is also being delineated in this project. The number of adders and multipliers are reduced by folding technique and thus increases the area efficiency of the filter. Simulations are carried out using soft wares like ModelSim SE 6.2c. The desired architecture is synthesized in Xilinx ISE Design Suite 14.2 and analysed the performance. © Research India Publications.