Publication Type:

Journal Article

Source:

International Journal of Applied Engineering Research, Research India Publications, Volume 10, Number 55, p.610-614 (2015)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84942310527&partnerID=40&md5=78514bb1f1bf3bde95c842153e33db56

Abstract:

The project focuses on the implementation of an n-tap Biquadratic filter using modified booth multiplier. The proposed multiplier deploys an efficient method to multiply two signed binary numbers in two’s complement. It uses radix- 4 algorithm which reduces the number of partial products which improves the speed of the booth multiplier. An effective algorithm where the multiplier consumes very less power is also being delineated in this project. The number of adders and multipliers are reduced by folding technique and thus increases the area efficiency of the filter. Simulations are carried out using soft wares like ModelSim SE 6.2c. The desired architecture is synthesized in Xilinx ISE Design Suite 14.2 and analysed the performance. © Research India Publications.

Notes:

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Cite this Research Publication

K. Jayaprakash, Mohan, A., Nair, A. G., and Nair, A. S., “Biquad filter design using booth multiplier and folding technique”, International Journal of Applied Engineering Research, vol. 10, pp. 610-614, 2015.