Publication Type : Journal Article
Publisher : Elsevier BV
Source : Memories - Materials, Devices, Circuits and Systems
Url : https://doi.org/10.1016/j.memori.2024.100108
Keywords : Bipolar transistors, Doping-free devices, Mixed signal applications, Memory performance, Reliability
Campus : Haridwar
School : School of Computing
Year : 2024
Abstract : Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain β values > 1100 , f t > 500 GHz, f m a x > 1300 GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of ∼ 1 . 3 ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the β value for WED-based devices when subjected to temperatures exceeding 340 K. In contrast, BED-based devices demonstrate a comparatively smaller variation in β at temperatures above 340 K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.
Cite this Research Publication : Abhishek Sahu, Abhishek Kumar, Anurag Dwivedi, Shree Prakash Tiwari, Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications, Memories - Materials, Devices, Circuits and Systems, Elsevier BV, 2024, https://doi.org/10.1016/j.memori.2024.100108