Publication Type:

Conference Paper

Source:

2009 International Conference on Computer and Electrical Engineering, ICCEE 2009, Volume 2, Dubai, p.503-506 (2009)

ISBN:

9780769539256

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-77950788554&partnerID=40&md5=6252c0638e6c30c553cfb0131e11f1b7

Keywords:

Bit-Width, Coarse-grained, Control bits, Data-intensive application, Electrical engineering, High flexibility, Low-power consumption, Multimedia signal processing, Power Consumption, Reconfigurable adder, Reconfigurable architecture, Signal processing, Verilog HDL

Abstract:

Reconfigurable architecture gives the advantage of both high performance and high flexibility. However power consumption is also an important criterion which determines the efficiency of the reconfigurable architecture to be used in data intensive applications like cryptography, multimedia and signal processing. This paper analyzes a coarse grained reconfigurable adder which can be dynamically reconfigured with respect to bitwidth of operands. Using multiplexers and appropriate control bits, part of the architecture may be powered-down according to the requirement, thereby saving power because of the inactive state of unused part. It is described in Verilog HDL and Synthesized on to Xilinx spartan-2 FPGA. Xilinx Xpower analyzer is used to find the power consumption. Experimental results of this design show the edge over existing design in terms of power consumption. © 2009 IEEE.

Notes:

cited By 1; Conference of 2009 International Conference on Computer and Electrical Engineering, ICCEE 2009 ; Conference Date: 28 December 2009 Through 30 December 2009; Conference Code:79725

Cite this Research Publication

Rajesh Kannan Megalingam, Popuri, G., and Ravisankar, P., “Low power consumption coarse grained reconfigurable adder”, in 2009 International Conference on Computer and Electrical Engineering, ICCEE 2009, Dubai, 2009, vol. 2, pp. 503-506.

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