Publication Type:

Journal Article

Source:

International Journal of Applied Engineering Research, Research India Publications, Volume 10, Number 55, p.679-684 (2015)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84942306940&partnerID=40&md5=a2599c67893856171ef961a07d8b6a17

Abstract:

This paper explains architectural design and performance of a DRAM, whose core cell consists of only two transistors using n-channel mosfets. Traditional Dram suffers from large latency times and an intricate refresh circuit. Since we have a benefit of density, on increasing its faster performance it can be used even in the operations held by the Static RAM. Its performance can be increased by interdivision of the banks into smaller sub-banks. On interdivision of banks even the latency time can be reduced. We have achieved a write and read cycle of 10ns. In view of the fact that the data is being read parallel, we need not have larger read cycles resulting in lesser cycle times contributing in high speed. The architecture has been implemented using cadence and plotted in mat-lab. Using this design of two transistors we have an advantage over single transistor cell in the areas of density and read types. On using multithread and multi-programmed workloads the Dram can be designed with better energy efficiency. Thus, the Dynamic RAM can replace the Static RAM combining the advantages of both fast access and high densities. © Research India Publications.

Notes:

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Cite this Research Publication

N. R. Chandra, Kusuma, C., Sarath, P., and Bhanu, R., “Low power high speed 1MB DRAM”, International Journal of Applied Engineering Research, vol. 10, pp. 679-684, 2015.