FIR plays a major role in today’s communication systems. The more advanced the implementation of the FIR filters become, the more efficient our communication systems become. The major components in FIR filter are multiplier, adder and delay elements. Multiplier circuits play a major role in deciding delay, speed and power in FIR filters. The way that the partial products are generated or summed up is the difference between the different architectures of various multipliers. To reduce the number of partial products, booth algorithm has been adopted and to improve the speed, conventional Wallace tree adder is introduced. To reduce the latency, power consumption and area, both Booth algorithm and Wallace tree techniques are combined to form a Booth Encoded Wallace Tree Multiplier. In addition with that pipelining and parallel processing are done to improve the speed while sacrificing area and latency. Using FDA with available stop-band and pass-band frequencies, the optimum coefficients and number of taps (N) are obtained. The Verilog and MATLAB codes for 16x16 to 24x24 bits of booth encoded Wallace tree multiplier have been done in order to get the optimum number of bits for implementing efficient FIR filter on comparing quantization noise. This paper proposes an efficient method to design an N- tap FIR filter using a compact Booth Encoded Wallace Tree multiplier in Verilog and verified in MATLAB. The 3 tap of proposed filter is also synthesized in Cadence tool. Then the performance deciding factors such as area, power and speed are calculated using the Xilinx. © Research India Publications.
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K. Sivaranjini, Jacob, N. S., Unnikrishnan, G., and Heera, K. H., “Low power, high speed FIR filter design”, International Journal of Applied Engineering Research, vol. 10, pp. 440-444, 2015.