This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction by reducing unwanted transitions. Verilog design followed by synthesis on to Xilinx spartan-3E FPGA was done. On-chip distributed memory of Spartan-3E was used for the data and the program memory implementations.
P. Gautham, Parthasarathy, R., and Dr. Karthi Balasubramanian, “Low-power pipelined MIPS processor design”, in Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC '09, 2009.