Publication Type:

Conference Paper

Source:

Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC '09, IEEE (2009)

ISBN:

9789810824686

Accession Number:

11105421

URL:

http://ieeexplore.ieee.org/abstract/document/5403912/

Keywords:

Communication system control, control logic, data forwarding units, data path, design engineering, Field programmable gate arrays, Hardware, hazard detection, Hazards, Logic, Logic design, Low Power Architecture, low power five-stage parallel pipelined structure, low-power electronics, low-power pipelined MIPS processor design, Microprocessor chips, MIPS Processor, MIPS-32 compatible CPU, on-chip distributed memory, Parallel Pipeline, pipeline processing, Power dissipation, Power engineering and energy, power reduction, Process design, program memory, registers, Verilog design, Xilinx spartan-3E FPGA

Abstract:

This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction by reducing unwanted transitions. Verilog design followed by synthesis on to Xilinx spartan-3E FPGA was done. On-chip distributed memory of Spartan-3E was used for the data and the program memory implementations.

Cite this Research Publication

P. Gautham, Parthasarathy, R., and Dr. Karthi Balasubramanian, “Low-power pipelined MIPS processor design”, in Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC '09, 2009.

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