This paper shows that not every scan cell contributes equally to the power consumption during scan based test. The transitions at some scan cells cause more toggles at the internal signal lines of a circuit, which have a larger impact on the power consumption during test application than the transitions at other scan cells. They are called power sensitive scan cells. A verilog based approach is proposed to identify a set of power sensitive scan cells. Additional hardware is added to freeze the outputs of power sensitive scan cells during scan shifting in order to reduce the shift power consumption. © 2011 Springer-Verlag.
cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@3c0fc9cc ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@30898ee2 Through org.apache.xalan.xsltc.dom.DOMAdapter@1703b053; Conference Code:84611
P. Reshma, “Scan based sequential circuit testing using DFT advisor”, Communications in Computer and Information Science, vol. 147 CCIS, pp. 203-206, 2011.