Publication

Abstract : The performance of thin body doping-free bipolar transistors on SOI are demonstrated for logic gates circuit using differential pass transistor logic. Charge carriers are induced inside the lightly doped SOI layer by using charge plasma (CP) and polarity control (PC) approaches. The study analyzes the transient, power, and noise margins of logic gates i.e., AND, OR and XOR gates designed using four device configurations i.e., CP based npn, CP based pnp, PC based npn, and PC based pnp. The results of these analyses are compared to prior studies of doping-free device-based circuits. The transient analysis indicates rise and fall time less than 50 ps and average switching power less than 5 µ W. The worstcase noise margin observed for 1 V input level is 0.28 V. Additionally, a 2:1 multiplexer is also designed and examined for response time and output voltage levels. For high logic, worst case output was 0.88 V, while for low logic, it was 0.05 V. The multiplexer took less than 1.8 ns to produce the output.