Publication Type:



Volume US6933219 B1, Number US 10/716,209 (2005)



<p>The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.</p>

Cite this Research Publication

Dr. Krishnashree Achuthan, Lingunis, E. H., Van Ngo, M., Tabery, C., and Yang, J. Y., “Tightly spaced gate formation through damascene process”, U.S. Patent US 10/716,2092005.

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