Course

Unit 1:

Fundamentals of DFM and Manufacturing Constraints – Introduction to VLSI scaling and DFM importance – Process variations: inter/intra-die, random/systematic – Yield loss mechanisms and yield modeling – Lithography limitations, RET (OPC, PSM), DRC vs model-based checks

Unit 2:

DFM-Aware Layout and Cell Design – Layout techniques: redundancy, dummy fills, antenna rules – Stress-aware and CMP-aware layout – Standard cell design with DFM in mind – Routing strategies: jogs, spacing, via optimization – Density rules, IR drop, electromigration, signal integrity

Unit 3:

Variation-Aware Design and EDA Tool Integration – Statistical design and variability modeling – Corner analysis, Monte Carlo simulation – DFM-aware P&R and sign-off –
Tool flows: Calibre DFM, Synopsys IC Validator, Cadence PVS – FinFET-aware design, machine learning for DFM, DTCO

Course Objectives

• Understand process technology constraints affecting VLSI design.
• Learn layout-level techniques to improve yield and performance.
• Develop skills to optimize designs for manufacturability and variability.
• Understand the impact of scaling and FinFET-era challenges on manufacturability.

Course Outcomes: At the end of the course, the student should be able to:

• CO1: Explain the impact of process variations and manufacturing constraints on VLSI design.
• CO2: Apply DFM rules and techniques to optimize physical layout for improved yield and manufacturability.
• CO3: Analyze and simulate the effects of parasitics, lithography limitations, and metal density on circuit reliability and performance.
• CO4: Evaluate DFM strategies using EDA tools and incorporate variation-aware design principles in the physical design flow.

Skills Acquired: Provide an in-depth knowledge on Design for Manufacturability

CO-PO Mapping:

1. Sandeep Kundu and Aswin Sreedhar, Nanoscale CMOS VLSI Circuits – Design for Manufacturability, McGraw-Hill, 2010.
2. Charles C Chiang and Jamil Kawa, Design for Manufacturability and Yield for Nano-scale CMOS, Springer 2007.
3. Ban Wong, Franz Zach, Victor Moroz, Anurag Mittal, Greg Starr, Andrew Kahng, Nano-CMOS Design for Manufacturability, John Wiley & Sons, 2009.
4. Artur Balasinski, Semiconductors Integrated Circuit Design for Manufacturability, CRC Press (Taylor and Francis), 2012.