Meena Belwal currently serves as Assistant Professor at department of Computer Science,Amrita School of Engineering.She is currently pursuing her Ph.D.


Publication Type: Conference Paper

Year of Publication Publication Type Title


Conference Paper

K. S. M and Meena Belwal, “Performance Dashboard Cutting-Edge Business Intelligence and Data Visualization”, in International Conference On Smart Technologies For Smart Nation (SmartTechCon2017), Reva University, Bengaluru, 2017.


Conference Paper

Meena Belwal, Dr. Madhura Purnaprajna, and Dr. T.S.B. Sudarshan, “Enabling seamless execution on hybrid CPU/FPGA systems: Challenges amp; directions”, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.[Abstract]

Today's computing systems are heterogeneous, with diverse micro-architectures. It is common to design systems comprising multi-core CPUs, Digital Signal Processors (DSP) and Graphic Processing Units (GPUs). In addition to these devices, the extensive configurability and parallelism in Field Programmable Gate Arrays (FPGAs) has proven to be advantageous for accelerating complex computational problems. In comparison to CPUs, DSPs and GPUs, FPGAs have a distinctly different microarchitecture. In this context, enabling seamless application execution in a system composed of FPGAs alongside CPUs, is a major challenge. As a consequence, simplifying programmability of hybrid CPU/FPGA systems demands innovations in system software support. There has been research in extending the traditional CPU-only system techniques to CPU/FPGA based hybrid systems to make way for FPGA-based mainstream computing. This article surveys techniques in dynamic task management aimed at reducing or completely eliminating the burden of operating system writers for CPU/FPGA hybrid systems and provide insight to researchers to explore further. More »»


Conference Paper

Meena Belwal and TSB, S., “Intermediate representation for heterogeneous multi-core: A survey”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Amrita School of Engineering, Bengaluru., 2015.[Abstract]

One of the necessary conditions to gain performance improvement through heterogeneous multi-core is to exploit the parallelism in the program. Compiler applies various transformations to the code to achieve execution efficiency. Code optimization is one of the important tasks performed by the compiler before generating the target code. With the availability of various parallel programming models in literature, Intermediate representation (IR) is the key point of applying several optimizations. IR is a form of program which is independent of the source language and the target architecture. There are several IR techniques specifically designed for each compiler framework depending on the input programming language. This article studies the most popular IR techniques for heterogeneous multi-core, classifies them into three broad categories and performs a comparison among them based on the data structure used and their importance in academia and research.

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Conference Paper

Meena Belwal and Sudarshan, T. S. B., “A survey on design space exploration for heterogeneous multi-core”, in 2014 International Conference on Embedded Systems (ICES), Coimbatore, India, 2014.[Abstract]

Design Space Exploration (DSE) plays an important role during the process of Hardware/Software co-design for heterogeneous multi-core architecture. DSE is the process of discovering and evaluating design alternatives, prior to implementation. The various designs can be compared with each other on the basis of required metrics and the optimized design can then be chosen to develop the system. The main goal of DSE is rapid prototyping and it is also used to find configurations and legal assemblies to satisfy a particular set of overall design constraints. This paper surveys the various DSE approaches used for heterogeneous multi-cores and compares them.

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NIRF 2018