Ph.D, M.E
+91 9446944312

Dr. Harish Ram D. S. currently serves as Assistant Professor at the department of Electronics and Communication Engineering, School of Engineering, Coimbatore Campus. He joined AAmrita Vishwa Vidyapeetham in 2008. His areas of research include Low Power VLSI Design, VLSI Architectures and Digital System Design.

Dr. Harish is a life member of IETE and ISTE.


Qualification College  University  Year
Ph. D. PSG College of Technology Anna University, Chennai 2014
M.E. (Applied Electronics) PSG College of Technology Bharathiar University 2000
B. Tech. (ECE) NSS College of Engineering University of Calicut 1993


Year Affiliation
2008 – Present Assistant Professor, Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore.
2003 – 2008 Assistant Professor (ECE), VLB Janakiammal College of Engg, Coimbatore.
2000 – 2003 Project Leader (VLSI Design), Accel Technologies, Chennai.
1994 – 1997 Senior Engineer (QA), BPL Telecom, Palakkad.

Membership in Professional Bodies

  • Life Member IETE, ISTE


  • VLSI System Design using HDLs
  • Computer Architecture
  • VLSI Architectures for Hardware Security and Trust
  • Digital System Design
  • Low Power VLSI Design
  • Hardware Software Codesign of Digital Systems
  • FPGA Based Honeypot design
  • Machine Learning approaches for FPGA accelerated malware analysis


Areas of Interest

TAG Group: VLSI – Computing, Hardware Systems and Architectures

  • Architectures for security and trust in cyber physical systems
  • Unconventional computing
  • Energy efficient Design

Research Projects

  • Architectures for data integrity assurance in smart metering systems
  • Application of Machine Learning for security in Cyber Physical Systems
  • FPGA based malware detection for high speed networks (under IBM Shared University Research (SUR) Program)

Research Expertise

  • Ongoing PhD works : Data Integrity in Cyber Physical Systems, Mr A Jayanth Balaji


PG Projects

  • FPGA Based Honeypot design
  • Machine Learning approaches for FPGA accelerated malware analysis.

Funded Projects

  • Malware Detection using FPGA, Sandboxing and Machine Learning funded by IBM for $ 12000 (jointly with Centre for Cyber Security and Dept of CSE)


Publication Type: Book Chapter

Year of Publication Title


M. C. Bhuvaneswari, Dr. Harish Ram D. S., and Neelaveni, R., “Design Space Exploration for Scheduling and Allocation in High Level Synthesis of Datapaths”, in Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems, M. C. Bhuvaneswari, Ed. New Delhi: Springer India, 2015, pp. 69–92.

Publication Type: Journal Article

Year of Publication Title


J. Balaji A. and Dr. Harish Ram D. S., “FPGA BASED SYSTEM FOR DENIAL OF SERVICE DETECTION IN SMART GRID”, ARPN Journal of Engineering and Applied Sciences, vol. 10, 2015.[Abstract]

The availability of cheap computing power and instrumentation electronics accompanied by the communication revolution has engendered a complete paradigm shift in the design and implementation of electrical grids. Power grids are envisaged to be transformed into “Smart Grids” incorporating a high degree of intelligence with a view to enhance the reliability and efficiency of generation, transmission and distribution systems. Real-time monitoring of grid parameters enables more effective management of power generation. Prevention of theft by means of smart metering is another major advantage. However, the large scale use of embedded systems, computing resources and communication networks makes the grid vulnerable to cyber attacks. These vulnerabilities can result in consequences ranging from diminished quality of service to catastrophic events such as line trips, extended blackouts and downright damage or destruction of assets. This paper gives a review of the current state-of-the art in cyber security for the smart grid environment. An FPGA based engine for detection of denial-of-service attacks in packets in an Ethernet link is also proposed.

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P. Dhanesh and Dr. Harish Ram D. S., “A fast and scalable pattern matching scheme for NIDS using Z algorithm”, International Journal of Applied Engineering Research, vol. 10, pp. 37563-37568, 2015.[Abstract]

Network Intrusion Detection Systems (NIDS) have become integral to today’s computer networks as the information transferred through the network is highly vulnerable to cyber-attacks. The implementation of the same involves an efficient string matching algorithm which will compare certain parameters and features of the received packets depending on the protocols used for communication. As the system incorporates a huge number of pattern comparisons, the string matching algorithm stands as the heart of entire NIDS system. Software implementations such as SNORT are inadequate for Ethernet backbones with bit rates of hundreds of Gigabits where high throughputs are required. Small improvements at the algorithmic level can boost the performance of the system drastically. In order to handle the large payloads of current network packets, simple and commonly used algorithms such as Aho-Corasick lack performance. In this work, the Z algorithm which is generally used for finding large subsequences in DNA strands is adapted for string matching for intrusion detection. This new algorithm shows noticeable improvements in performance and scalability. © Research India Publications.

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Dr. Harish Ram D. S., Umadevi, S., and Bhuvaneswari, M. C., “Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection”, Advances in Electrical and Computer Engineering, vol. 13, pp. 85-92, 2013.


Dr. Harish Ram D. S., Bhuvaneswari, M. Cb, and Prabhu, S. Sa, “A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths”, VLSI Design, vol. 2012, 2012.[Abstract]

High-Level Synthesis deals with the translation of algorithmic descriptions into an RTL implementation. It is highly multi-objective in nature, necessitating trade-offs between mutually conflicting objectives such as area, power and delay. Thus design space exploration is integral to the High Level Synthesis process for early assessment of the impact of these trade-offs. We propose a methodology for multi-objective optimization of Area, Power and Delay during High Level Synthesis of data paths from Data Flow Graphs (DFGs). The technique performs scheduling and allocation of functional units and registers concurrently. A novel metric based technique is incorporated into the algorithm to estimate the likelihood of a schedule to yield low-power solutions. A true multi-objective evolutionary technique, "Nondominated Sorting Genetic Algorithm II" (NSGA II) is used in this work. Results on standard DFG benchmarks indicate that the NSGA II based approach is much faster than a weighted sum GA approach. It also yields superior solutions in terms of diversity and closeness to the true Pareto front. In addition a framework for applying another evolutionary technique: Weighted Sum Particle Swarm Optimization (WSPSO) is also reported. It is observed that compared to WSGA, WSPSO shows considerable improvement in execution time with comparable solution quality. © 2012 D. S. Harish Ram et al.

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Publication Type: Conference Paper

Year of Publication Title


Dr. Harish Ram D. S., Srinivasan, S., Srinikethan, M. S., and Dr. Shanmugha Sundaram G. A., “3-D stack of waveguide structures with hour-glass slot structure for terahertz antenna applications”, in 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, 2015, pp. 689-693.[Abstract]

The design of an antenna using metamaterials (MTM) for usage in the Terahertz frequency range is presented here. A detailed analysis of the ω-β curves, scattering (S) parameters and radiation patterns is done for a Composite Right/Left Handed (CRLH) transmission line metamaterials designed as a metal-metal (MM) waveguide that incorporates an hour glass slot unit cell structure. An array of the same in two dimension is studied next. This is followed by a study of the 3D stacked structure of the same MM-MTM. A final design configuration is proposed for application in active antenna systems. © 2015 IEEE.

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Dr. Harish Ram D. S., Bhuvaneswari, M. Cb, and Logesh, S. Ma, “A novel evolutionary technique for multi-objective power, area and delay optimization in High Level Synthesis of datapaths”, in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, 2011, pp. 290-295.[Abstract]

The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology for area, power and delay optimization using the Non-dominated Sorting Genetic Algorithm II (NSGA II). A metric based technique has been used to determine the likelihood of a schedule to yield low power solutions during binding. Actual power numbers are not determined since this is computationally expensive. The methodology has been evaluated on standard benchmark Data-Flow Graphs (DFGs) and results indicate that it yields improved solutions with better diversity when compared to a weighted sum GA approach. For the IIR benchmark, it was observed that the NSGA II was able to converge to the true Pareto front obtained from exhaustive search. © 2011 IEEE.

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A. S. Yazhini and Dr. Harish Ram D. S., “High level synthesis of data flow graphs using integer linear programming for switching power reduction”, in 2011 - International Conference on Signal Processing, Communication, Computing and Networking Technologies, ICSCCN-2011, Thuckalay, 2011, pp. 475-479.[Abstract]

This paper seeks to investigate integer linear programming (ILP) methodologies for power optimization during high level synthesis (HLS). Scheduling, binding and allocation are the three basic steps in high level synthesis. Here power aware scheduling and binding are considered. Integer Linear Programming has been widely investigated for solving scheduling and binding problems. Various methods are available for solving integer linear programming problems. There are several issues encountered in ILP like scalability and computational complexity. In this paper, an existing ILP approach for power aware scheduling of data flow graphs (DFGs) has been modified with a simpler set of constraint specifications. To devise the ILP, constraints are specified by means of matrices that are consequential from the data flow graph (DFG) and switching activity information. From that DFG, two matrices are generated based on the intra and inter iteration precedence of the nodes. Another input matrix is also derived from the data flow graph based on the switching activity information. Constraints related to time steps and node execution steps are specified by means of inequalities. All input matrices required for the ILP Formulation are generated using C with the data flow graph as input. FICO Xpress optimization suite is used for executing the ILP. Preliminary results indicate that the proposed modified ILP approach results in shorter execution times. © 2011 IEEE. More »»

Publication Type: Conference Proceedings

Year of Publication Title


N. A. Nikhil and Dr. Harish Ram D. S., “Hardware implementation of quasigroup based encryption”, Proceedings of International Conference on Embedded Systems (ICES). pp. 55-58, 2014.