Ph.D, M.Tech

Dr. Ganapathi Hedge currently serves as Assistant Professor(SG) at department of Electronics and Communication,Amrita School of Engineering.

Ganapathi Hegde received his B.E. degree in Electronics and Communication from the University of Mysore, India, in 1998 and his M.Tech. degree in Digital Electronics from Visweswaya Technological University, Belgaum, India, in 2001. From 2001 to 2005, he worked as a lecturer at the Manipal Institute of Technology, India. Since 2005, he has been working as an Assistant Professor with the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Bangalore, India. His main research interests are VLSI architectures for video processing, ASIC design, and Low‐Power VLSI design.


  • 2018: Ph. D.
    Amrita Vishwa Vidyapeetham, India
  • 2001: M. Tech.
    V. T.U. Belgaum, India
  • 1998: B. E.
    University of Mysore, India

Professional Appointments

Year Affiliation
2001 K. S. Institute of Technology, Bangalore, INDIA
2002 Manipal Institute of Technology, Manipal, INDIA
2005 School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru Campus, INDIA

Membership in Professional Bodies

  • IEEE
  • TETE
  • IE
  • ISTE


Publication Type: Conference Paper

Year of Publication Title


S. Jagata, Ganapathi Hegde, and Murty, N. S., “High Throughput Pipelined S-Boxes for Encryption and Watermarking Applications”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, 2020.[Abstract]

In the Advanced Encryption Standard Algorithm, S-box is a fundamental step. In this paper, three new S-box architectures are introduced and implemented with pipelining. They are Combined, Inverse, and Forward S-boxes. Each S-box represents a lower delay and higher throughput. This goal is achieved by pipelining and optimizing each block inside the three proposed architectures. Our designs outpace others in terms of throughput and delay. The PSNR rate is better than other designs. The proposed S-boxes are implemented in encryption and watermarking applications. The behavior of pipelined S-boxes under few attacks is also observed.

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M. Sagar and Ganapathi Hegde, “FPGA Implementation of 8-bit SSA Multiplier for designing OFDM Transceiver”, in 2019 International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2019.[Abstract]

In recent technology of digital signal processing applications, we have number of modulation and demodulation techniques. In this domain multiplexing technique is having greatest importance as it has a transmission and reception part with secure systems for communication. Thus orthogonal frequency division multiplexing (OFDM) is superior to other multiplexing techniques, which has multiple carriers with very much robust frequency selective distorted channels. OFDM will have a number of modules such as serial to parallel converter, modulator, IFFT, FFT, demodulator and so on. The Proposed work will concentrate on arithmetic operations in OFDM with re-modified technique using large integer values such as addition, and multiplications. This large integer based arithmetic operation technique were designed using Schönhage-Strassen algorithm (SSA). Thus the proposed method will focus on this SSA algorithm based arithmetic operations with Number Theoretic Transform (NTT) and Inverse Number Theoretic transform (INTT) method. Proposed method of OFDM will replace FFT-IFFT to NTT-INTT method and this application is developed in Verilog HDL and synthesized in Xilinx vivado 15.4. It proved better results in terms of area and delay when compared with conventional design.

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R. Manasa, Ganapathi Hegde, and M. Vinodhini, “Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques”, in 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Msyuru, India, 2018.[Abstract]

System on Chip (SoC) process technology is shrinking day by day resulting in increased complexity. In the presence of faults, the reliability of embedded memories in deep submicron technology is becoming a significant challenge. Embedded Memories are highly prone to soft errors and hard faults. Hence, hard repair techniques combined with Error Correction Codes (ECCs) can improve the reliability of embedded memories. An integrated ECC and Built-In Self-Repair (BISR) technique is proposed in this paper can correct 8 faulty bits for a 16-bit input. Higher error correction and repair capability gives the higher reliability. The proposed integrated ECC and BISR has less area and more faulty bit correction capability compared to Enhanced Built -In Self-Repair (EBISR) technique.

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Ganapathi Hegde, Reddy, K. Srinivasa, and Dr. T. K. Ramesh, “An approach for area and power optimization of flipping 3-D discrete wavelet transform architecture”, in 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017.[Abstract]

In this work, an approach for optimizing the 3-D Discrete wavelet transform (3-D DWT) architecture is recommended. Conventional 3-D DWT architectures include basic building blocks such as 1-D DWT module, 2-D DWT module, transpose memory unit, and temporal memory unit. Proposed 3D DWT architecture is designed by suitably interconnecting the fundamental constituents (1-D DWT and 2-D DWT modules) which do not demand transposition and temporal memory units. Architecture employing the recommended approach is realized in gate level Verilog HDL. Design is functionally verified, synthesized using Cadence RC design compiler, and implemented on 90nm standard cell library. Experimental results exhibit that the proposed approach for the architecture offers significant gain in both area and power.

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R. Mithun and Ganapathi Hegde, “High performance VLSI architecture for 2-D DWT using lifting scheme”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]

Reduced area and high speed 2-D DWT structural design is presented here. To decrease the delay in critical path with one multiplier, minimum stages of pipeline stage required are four for a lifting step. To reduce the pipeline stages, here short modification is adopted by recombining and storing the intermediate stages of result value. By adopting this work, we can reduce register number without critical path extension and scanning architecture adopted is parallel two inputs/ two outputs architecture, and it increases the speed and critical path can be decreased to a delay of a multiplier by 3 pipeline stages. By adopting shift add method for multiplication, the proposed method able to decrease the delay in critical path to delay of a adder. The number of registers between column and row filter requires is three for this proposed architecture for NXN size 2-DWT. © 2015 IEEE.

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R. Bhaskar, Ganapathi Hegde, and Vaya, P. R., “An efficient hardware model for RSA encryption system using Vedic mathematics”, in Procedia Engineering, Coimbatore, 2012, vol. 30, pp. 124-128.[Abstract]

The standard techniques for providing privacy and security in data networks include encryption/decryption algorithms such as Advanced Encryption System (AES) (private-key) and RSA (public-key). RSA is one of the safest standard algorithms, based on public-key, for providing security in networks. Even though the RSA Algorithm is an old and simple encryption technique, there is a scope to improve its performance. One of the most time consuming processes in RSA encryption/ decryption algorithm is the computation of ab mod n where "a" is the text, (b, n) is the key. Generally the prime number used for RSA Encryption system will around 100 to 150 decimal digits. The computations involved are tedious and time consuming. Also the hardware is quite complex. To increase the computation speed, the multiplication principle of Vedic mathematics is used and also an improvement is made in the conventional restoring algorithm which does the modulus operation. "Urdhva- tiryakbhyam" is the sutra (principle) which used to compute the multiplication. It literally means vertical and crosswise manipulation. The significance of this technique is that it computes the partial products in one step and avoids the shifting operation which saves both time and hardware. Also an improvement is made in the restoring algorithm by avoiding unnecessary restorations when they are not required.

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Ganapathi Hegde and Vaya, P., “An efficient distributive arithmetic based 3-dimensional discrete wavelet transform for video processing”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]

This paper presents an efficient Distributive arithmetic (DA) based parallel processor based architecture to realize 3-Dimensional Discrete wavelet transform (3-D DWT) architecture. Basic DA is modified suitably to employ in 3-D DWT. Parallel processing DA architecture employing modified DA algorithm is designed, modeled and implemented on FPGA. The modified DA reduces the storage space and power consumption by 93% and 4% respectively. The parallel processing 3-D DWT architecture realized using modified DA produces a time delay of 65ns and consumes a power of 108mW. The designed parallel processing based 3-D DWT architecture can be used for video processing applications. © 2011 IEEE. More »»

Publication Type: Journal Article

Year of Publication Title


Ganapathi Hegde, Reddy, K. S., and Dr. T. K. Ramesh, “A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell”, AEU - International Journal of Electronics and Communications, vol. 97, pp. 165-177, 2018.[Abstract]

In this paper, area and power efficient lifting and flipping discrete wavelet transform (DWT) architectures are proposed. DWT architectural metrics such as critical path delay, area of utilization, power consumption are mainly dependent on the arithmetic components such as adders and multipliers. They constitute the data-path of the DWT structure. A multiplier of the DWT data-path plays major role in basic lifting, flipping cells and further it demands optimization. In this work, an area and power efficient lifting and flipping cells are implemented using look up table (LUT) based multipliers. The proposed DWT architectures are implemented in gate level Verilog HDL and are synthesized using Cadence RC design compiler. Based on the area, delay, and power results obtained from post synthesis, parameters like area delay product (ADP) and power delay product (PDP) are computed. The ADP and PDP values prove that the proposed LUT based architectures are efficient over recently projected lifting and flipping DWT architectures. © 2018 Elsevier GmbH

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Ganapathi Hegde, Krishna, R. S. Amritha, and Vaya, P., “Conservative approximation-based full-search block matching algorithm architecture for QCIF digital video employing systolic array architecture”, ETRI Journal, vol. 37, pp. 772-779, 2015.[Abstract]

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency. © 2015 ETRI.

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Ganapathi Hegde and Vaya, P., “A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding”, International Journal of Electronics, vol. 100, pp. 1429-1440, 2013.[Abstract]

This article presents a parallel architecture for 3-D discrete wavelet transform (3-DDWT). The proposed design is based on the 1-D pipelined lifting scheme. The architecture is fully scalable beyond the present coherent Daubechies filter bank (9, 7). This 3-DDWT architecture has advantages such as no group of pictures restriction and reduced memory referencing. It offers low power consumption, low latency and high throughput. The computing technique is based on the concept that lifting scheme minimises the storage requirement. The application specific integrated circuit implementation of the proposed architecture is done by synthesising it using 65 nm Taiwan Semiconductor Manufacturing Company standard cell library. It offers a speed of 486 MHz with a power consumption of 2.56 mW. This architecture is suitable for real-time video compression even with large frame dimensions. © 2013 Taylor and Francis Group, LLC.

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Ganapathi Hegde and Vaya, P., “Systolic array based motion estimation architecture of 3D DWT sub band component for video processing”, International Journal of Signal and Imaging Systems Engineering, vol. 5, pp. 158-166, 2012.[Abstract]

This paper describes Full Search Block Matching Algorithm (FSBMA) performed on 3D image in the transformed domain. An image of size N×N×8 is first transformed in to eight sub bands each of size N/2 × N/2 × 4 employing 3D Discrete Wavelet Transform (3D DWT). FSBMA performed on LLL sub band component which achieves good Peak Signal to Noise Ratio (PSNR), Compression Ratio (CR) and reduces computation complexity when compared with the original image. Modified lifting scheme based DWT and Systolic Array Architecture (SAA) based FSBMA are implemented on Field Programmable Gate Array (FPGA). 3D DWT implemented on FPGA operates at 230 MHz and consumes a power of 0.29 W, while FSBMA implemented on FPGA to reduce the computational time for motion estimation, operates at 120 MHz and consumes a power less than 0.34 W. Copyright © 2012 Inderscience Enterprises Ltd.

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Ganapathi Hegde and Vaya, P., “An efficient 3-dimensional discrete wavelet transform architecture for video processing application”, Journal of Electronics, vol. 29, pp. 534-540, 2012.[Abstract]

This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0. 45 W. © 2012 Science Press, Institute of Electronics, CAS and Springer-Verlag Berlin Heidelberg.

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Courses Taught

  • VLSI Design
  • Pattern Recognition and Algorithms
  • Sensors and Systems
  • Linear Integrated Circuits
  • VLSI Signal Processing
  • Computer System Architectures
  • Digital Signal Processing

Student Guidance

Undergraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 K. Teja
B. Vani
Intelligent safety system for women security using Raspberry Pi Completed 2020
2 Ram Pradeep A
Ranga Sridhar
Real Time Adaptive Traffic Control System Completed 2020
3 Sampath Kumar
S V Sandeep
S Akhil
High performance- based face detection system using FPGA Completed 2019
4 Raghava Krishna Manoj Competitive Intelligence Completed 2018
5 M. Tejaswi A Key Account Prioritization Completed 2018
6 N. Chanadana
G. V. Divya Sai
M. V. N. S. Rohita
VLSI Implementation of IP Core for 4G long Term Evolution OFDM/FDMA Completed 2018
7 D. Venkateswara Raju
G. Venkata Naga Deepak
K. Jaya Sesha Sai Nikhil
ANDROID studio applications Completed 2017

Postgraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Sridevi Jagata High Throughput Pipelined S-Boxes for Encryption and Watermarking Applications Completed 2020
2 Mallapareddi Sagar FPGA Implementation of 8-bit SSA Multiplier for designing OFDM Transceiver Completed 2019
3 Manasa, R Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques Completed 2018

Research Scholars

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Ms. Rasiraju Sankeerthana VLSI Signal Processing Ongoing NA
2 Ms. Chitralekha G Image Processing Ongoing NA
3 Mr. Ravikumar Tiwari, Machine Learning Ongoing NA
4 Mr. Krishna K.S Machine Learning Applications of Transforms Ongoing NA
5 Mr. R. Swaminadhan Machine Learning Ongoing NA