Ganapathi Hedge currently serves as Assistant Professor(SG) at department of Electronics and Communication,Amrita School of Engineering.He is currently pursuing his Ph. D.









Publication Type: Conference Paper
Year of Publication Publication Type Title
2015 Conference Paper R. Mithun and Hegde, G., “High performance VLSI architecture for 2-D DWT using lifting scheme”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.[Abstract]

Reduced area and high speed 2-D DWT structural design is presented here. To decrease the delay in critical path with one multiplier, minimum stages of pipeline stage required are four for a lifting step. To reduce the pipeline stages, here short modification is adopted by recombining and storing the intermediate stages of result value. By adopting this work, we can reduce register number without critical path extension and scanning architecture adopted is parallel two inputs/ two outputs architecture, and it increases the speed and critical path can be decreased to a delay of a multiplier by 3 pipeline stages. By adopting shift add method for multiplication, the proposed method able to decrease the delay in critical path to delay of a adder. The number of registers between column and row filter requires is three for this proposed architecture for NXN size 2-DWT. © 2015 IEEE.

More »»
2012 Conference Paper R. Bhaskar, Hegde, G., and Vaya, P. R., “An efficient hardware model for RSA encryption system using Vedic mathematics”, in Procedia Engineering, Coimbatore, 2012, vol. 30, pp. 124-128.[Abstract]

The standard techniques for providing privacy and security in data networks include encryption/decryption algorithms such as Advanced Encryption System (AES) (private-key) and RSA (public-key). RSA is one of the safest standard algorithms, based on public-key, for providing security in networks. Even though the RSA Algorithm is an old and simple encryption technique, there is a scope to improve its performance. One of the most time consuming processes in RSA encryption/ decryption algorithm is the computation of ab mod n where "a" is the text, (b, n) is the key. Generally the prime number used for RSA Encryption system will around 100 to 150 decimal digits. The computations involved are tedious and time consuming. Also the hardware is quite complex. To increase the computation speed, the multiplication principle of Vedic mathematics is used and also an improvement is made in the conventional restoring algorithm which does the modulus operation. "Urdhva- tiryakbhyam" is the sutra (principle) which used to compute the multiplication. It literally means vertical and crosswise manipulation. The significance of this technique is that it computes the partial products in one step and avoids the shifting operation which saves both time and hardware. Also an improvement is made in the restoring algorithm by avoiding unnecessary restorations when they are not required.

More »»
2011 Conference Paper G. Hegde and Vaya, P., “An efficient distributive arithmetic based 3-dimensional discrete wavelet transform for video processing”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]

This paper presents an efficient Distributive arithmetic (DA) based parallel processor based architecture to realize 3-Dimensional Discrete wavelet transform (3-D DWT) architecture. Basic DA is modified suitably to employ in 3-D DWT. Parallel processing DA architecture employing modified DA algorithm is designed, modeled and implemented on FPGA. The modified DA reduces the storage space and power consumption by 93% and 4% respectively. The parallel processing 3-D DWT architecture realized using modified DA produces a time delay of 65ns and consumes a power of 108mW. The designed parallel processing based 3-D DWT architecture can be used for video processing applications. © 2011 IEEE. More »»
Publication Type: Journal Article
Year of Publication Publication Type Title
2015 Journal Article G. Hegde, Krishna, R. S. Amritha, and Vaya, P., “Conservative approximation-based full-search block matching algorithm architecture for QCIF digital video employing systolic array architecture”, ETRI Journal, vol. 37, pp. 772-779, 2015.[Abstract]

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency. © 2015 ETRI.

More »»
2013 Journal Article G. Hegde and Vaya, P., “A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding”, International Journal of Electronics, vol. 100, pp. 1429-1440, 2013.[Abstract]

This article presents a parallel architecture for 3-D discrete wavelet transform (3-DDWT). The proposed design is based on the 1-D pipelined lifting scheme. The architecture is fully scalable beyond the present coherent Daubechies filter bank (9, 7). This 3-DDWT architecture has advantages such as no group of pictures restriction and reduced memory referencing. It offers low power consumption, low latency and high throughput. The computing technique is based on the concept that lifting scheme minimises the storage requirement. The application specific integrated circuit implementation of the proposed architecture is done by synthesising it using 65 nm Taiwan Semiconductor Manufacturing Company standard cell library. It offers a speed of 486 MHz with a power consumption of 2.56 mW. This architecture is suitable for real-time video compression even with large frame dimensions. © 2013 Taylor and Francis Group, LLC.

More »»
2012 Journal Article G. Hegde and Vaya, P., “An efficient 3-dimensional discrete wavelet transform architecture for video processing application”, Journal of Electronics, vol. 29, pp. 534-540, 2012.[Abstract]

This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0. 45 W. © 2012 Science Press, Institute of Electronics, CAS and Springer-Verlag Berlin Heidelberg.

More »»
2012 Journal Article G. Hegde and Vaya, P., “Systolic array based motion estimation architecture of 3D DWT sub band component for video processing”, International Journal of Signal and Imaging Systems Engineering, vol. 5, pp. 158-166, 2012.[Abstract]

This paper describes Full Search Block Matching Algorithm (FSBMA) performed on 3D image in the transformed domain. An image of size N×N×8 is first transformed in to eight sub bands each of size N/2 × N/2 × 4 employing 3D Discrete Wavelet Transform (3D DWT). FSBMA performed on LLL sub band component which achieves good Peak Signal to Noise Ratio (PSNR), Compression Ratio (CR) and reduces computation complexity when compared with the original image. Modified lifting scheme based DWT and Systolic Array Architecture (SAA) based FSBMA are implemented on Field Programmable Gate Array (FPGA). 3D DWT implemented on FPGA operates at 230 MHz and consumes a power of 0.29 W, while FSBMA implemented on FPGA to reduce the computational time for motion estimation, operates at 120 MHz and consumes a power less than 0.34 W. Copyright © 2012 Inderscience Enterprises Ltd.

More »»
Faculty Details


Faculty Email: