Publication Type : Conference Paper
Publisher : Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011
Source : Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore (2011)
ISBN : 9781612847641
Keywords : 3-dimensional, Computer architecture, Delay control systems, Discrete wavelet transforms, Parallel processing, Parallel processor, Process control, Storage spaces, Three dimensional, Three dimensional computer graphics, Video processing, Video processing applications, Video signal processing
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2011
Abstract : This paper presents an efficient Distributive arithmetic (DA) based parallel processor based architecture to realize 3-Dimensional Discrete wavelet transform (3-D DWT) architecture. Basic DA is modified suitably to employ in 3-D DWT. Parallel processing DA architecture employing modified DA algorithm is designed, modeled and implemented on FPGA. The modified DA reduces the storage space and power consumption by 93% and 4% respectively. The parallel processing 3-D DWT architecture realized using modified DA produces a time delay of 65ns and consumes a power of 108mW. The designed parallel processing based 3-D DWT architecture can be used for video processing applications. © 2011 IEEE.
Cite this Research Publication : G. Hegde and Vaya, P., “An efficient distributive arithmetic based 3-dimensional discrete wavelet transform for video processing”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.