Swaminadhan R. currently serves as Assistant Professor at department of Electronics and Communication,Amrita School of Engineering, Banglore campus.


  • Ph. D. (pursuing) in VLSI Domain
    Amrita Vishwa Vidyapeetham
  • 2011: M. Tech. in  Microelectronics and VLSI Design
    NIT Calicut
  • 2007: B. Tech in Electronics and Communication Engineering
    Narayana Engineering College, Nellore

Research & Management Experience

  • 4 years’ experience on research


Publication Type: Conference Proceedings

Year of Publication Title


N. Varghese and Swaminadhan R., “Power Efficient Router Architecture for Scalable NoC”, Innovations in Electronics and Communication Engineering. Springer Singapore, Singapore, 2020.[Abstract]

A power efficient router architecture to increase the performance in a NoC interconnect is suggested in this paper. Static power reduction by using power-gating techniques has been extensively discussed in the past. More recent papers implement router architectures to resolve the issues in power gating such as early wake-up latency and energy dissipation, thereby achieving high performance and reduction in static power. The work proposed in this paper modifies on a recent router architecture that remedied the early wake-up latency overhead and achieved significant power savings. The proposed LPSQ router architecture provides an additional reduction in dynamic power and area overhead by 20.2% and 24.5%, respectively, without degrading the overall system performance.

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N. Rose Varghese and Swaminadhan R., “High Speed Low Power Radix 4 Approximate Booth Multiplier”, 2019 3rd International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech). IEEE, Kolkata, India, 2019.[Abstract]

Many applications such as image processing and multipliers are resilient to inexactness or approximations in their underlying computations. This is the basic concept of approximate computation. The resulting degradation in output quality can be traded off to develop more energy efficient and high performance hardware systems. In this context, approximate circuit design is an emerging paradigm that has recently received considerable research attention. Many applications such as signal processing and image processing requires the use of multipliers in its core operating system. The fundamental objective of a multiplier is that it must be efficient in power and operate at high speed. The aim is to design the best possible radix 4 booth multiplier using approximate computing. The work proposed in this paper is an extended application to an existing and recent work in approximate adder design SARA which is an Accuracy Configurable Adder (ACA). A radix 4 approximate booth multiplier application is proposed in this paper which has significant improvement in power, speed and accuracy compared to the earlier approaches in approximate booth multipliers. The comparison is performed with the conventional radix 4 booth multiplier and there is a 72% and 17% reduction in power and delay respectively.

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S. D Vishnu, Sowjanya, D. V., P Reddy, N., and Swaminadhan R., “Implementation and Design of optimized FIR filter using Radix-2r”, 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) . 2018.

Publication Type: Journal Article

Year of Publication Title


S. Shah, Swaminadhan R., G.R., M. Reddy, V.S., R., and V.K., P., “Design of FIR filter architecture for fixed and reconfigurable applications using highly efficient carry select adder”, Advances in Intelligent Systems and Computing, vol. 898, pp. 627-637, 2019.[Abstract]

With increased complexity in digital circuits, efficient performance of involved circuitry has become the part and parcel of the digital signal processors (DSPs). In this paper, we have designed an efficient FIR filter for fixed and reconfigurable applications by embedding an area, and delay efficient carry select adder (CSLA), implemented by optimizing the redundancies in the logical operations in conventional and BEC-based CSLA. The proposed CSLA involves less area and delay than BEC-based CSLA and conventional CSLA. Here the carry operation is scheduled before the ultimate sum unlike the traditional method. Having desirably less output area and delay this becomes the best choice for FIR filter of transpose form. For the reconfigurable filter design, it is seen that the delay is reduced by 26.66%, and for MCM-based filter, the delay is reduced by 20.23%. The efficacy of the proposed design is accompanied by 15% reduction in area. © Springer Nature Singapore Pte Ltd. 2019.

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Publication Type: Conference Paper

Year of Publication Title


S. Bodapati and Swaminadhan R., “An Efficient FIR Filter Architecture using 4:2 Compressor”, in International Conference on Intelligent Computing (ICIC) 2018, Amrita School of Engineering, Bengaluru, 2018.

Courses Taught

  • Network Theory/Circuit Theory
  • Electronic Circuits-I & II
  • VLSI Design
  • Applied Electromagnetics
  • Transmission Lines and radiating systems
  • Control systems engineering

Student Guidance

Undergraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1 Parakoti Venkata
Naga Sai Ganesh
Medipally Shiva
Rohith Reddy
Meruva Revanth Sai
Design of Power and Area Efficient Approximate Multiplier Ongoing 2021
2 P. Geetheswar
Y. Veerendra Sai
Palukuri Sumanth
Vehicle Detection and Traffic Density Controlling Using Artificial Neural Networks Ongoing 2021
3 P.Ch Sri Rama Seshu
P Sai Kiran
Design And Implementation of 128 X 128 Bit Multiplier By Vedic Mathematics Ongoing 2021
4 Gg Chowdary
P.Mukesh Satya Krishna
V.Ch.Satya Prakash
Conversion of Image to Text and Speech Completed 2020
5 M.Amulya
K. Thanushree
Efficiency of S-Box In Block Ciphers Completed 2020
6  Devireddy Sravya Eppiti Rishita Reddy  G.Venkata Abhiram3  Congestion Control And Collision Avoidance In Vehicular Area Networks Completed 2019
7 G.V. Amaranath Reddy,
G. Navya Sree,
J. N. S. Sarvani
Implementation of Efficient AES Algorithm in FPGA Architecture Completed 2019
8 D. S. Vishnu
D. V. Sowjanya
P. N. Reddy
Design of optimized FIR filter using Radix-2r Completed 2018
9 Santhoshkumar S D,
Samineni Akhil,
Sushanth Alapati
Modified Standard Basis Encoding And Decoding Technique Using Multiplexer Completed 2018

Postgraduate Students

Sl. No. Name of the Student(s) Topic Status – Ongoing/Completed Year of Completion
1  Duggi Niveditha  Implementation of Low Area ALU using Reversible Logic Formulations Completed 2020
2  Gopika Reji  Optimized Concurrent Error Detectable Adder Completed 2020
3 Nivya Varghese Power Efficient Router Architecture for Scalable NoC Completed 2019
4 Nivya Varghese High Speed Low Power Radix 4 Approximate Booth Multiplier Completed 2019
5 Saurav Shah Design of FIR Filter Architecture for Fixed and Reconfigurable Applications Using Highly Efficient Carry Select Adder Completed 2019
6 Boddapati Sainath An Efficient FIR Filter Architecture using 4:2 Compressors Complted 2019