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Publication Type : Conference Proceedings
Publisher : Innovations in Electronics and Communication Engineering
Source : Innovations in Electronics and Communication Engineering, Springer Singapore, Singapore (2020)
ISBN : 9789811531729
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2020
Abstract : A power efficient router architecture to increase the performance in a NoC interconnect is suggested in this paper. Static power reduction by using power-gating techniques has been extensively discussed in the past. More recent papers implement router architectures to resolve the issues in power gating such as early wake-up latency and energy dissipation, thereby achieving high performance and reduction in static power. The work proposed in this paper modifies on a recent router architecture that remedied the early wake-up latency overhead and achieved significant power savings. The proposed LPSQ router architecture provides an additional reduction in dynamic power and area overhead by 20.2% and 24.5%, respectively, without degrading the overall system performance.
Cite this Research Publication : N. Varghese and Swaminadhan R., “Power Efficient Router Architecture for Scalable NoC”, Innovations in Electronics and Communication Engineering. Springer Singapore, Singapore, 2020.