Qualification: 
Ph.D
s_kamatchi@blr.amrita.edu

Dr. Kamatchi S. currently serves as Assistant Professor (Sr. Gr.) at the department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru Campus.

She completed her Ph. D. in Low Power VLSI in September 2018 under Anna University, Chennai. She worked in Akshaya College of Engineering for past 10 years and prior to that she worked in Coimbatore Institute of Engineering and Technology for two and half years.

Education

  • 2018: Ph.D. in Low Power VLSI
    Anna University, Chennai

Publications

Publication Type: Conference Proceedings

Year of Publication Title

2021

D. Navaneet Rao, Degala, S. Ram, Charan, G. Sai, and Kamatchi S., “Posit Number Division using Newton Raphson Method”, International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies (ICAECT 2021). Department of Electrical and Electronics Engineering, Shri Shankaracharya Group of Institutions, SSTC, Bhilai, Chhattisgarh, India, 2021.

Publication Type: Conference Paper

Year of Publication Title

2020

P. Kumar and Kamatchi S., “A Secure, Area Efficient Strong Physical Unclonable Function Design using LFSR”, in 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, India, 2020.[Abstract]


The safety of electronic hardware devices is always remaining as a major concern in today’s world. With the expanding development of the microelectronics gadgets and application, there is a parallel squeezing more interest in guaranteeing these items’ genuineness, safety, and dependability of its electronic framework. The safety prerequisite for the majority part of these applications is significant and evolving nowadays, similar to this expansion in advance assaults are also build up each day. These assaults regularly have a lot higher effect and basically, no real way to make up for them with extra programming countermeasures on-chip “physical unclonable function (PUF)” are come out as an amazing safety alternative those can be conceivably taken care of security issue. In this paper, a “PUF” framework is proposed which is dependent on LFSR rationale that can be effortlessly executed on “FPGA”. Here another solid “PUF” plan is proposed, which is postponement based “PUF”. Defer based “PUF” utilizes worked in postpone qualities of the physical parts that are inalienable among chip to chip. Easily approval of “integrated circuits(IC)” depends on “PUF” utilization is portrayed. The entire venture is executed utilizing “Verilog HDL” and orchestrated with a “Xilinx Vivado2019.2”. The fundamental point of this task is to concentrate on, fewer areas of the design and relatively low power consumption. It can be smoothly implemented and the right choice for “device authentication” on “FPGA”.

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2019

V. Harish and Kamatchi S., “Comparative Performance Analysis of Karatsuba Vedic Multiplier with Butterfly Unit”, in 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.[Abstract]


In DSP processors or other applications which use multiply-accumulate units (MAC) etc., multiplication of large numbers is the main bottleneck. Multiplying two n-bit binary numbers requires n (n - 1 ) adders and n2 AND gates, which consumes more time, power and area for large n since the hardware scales as the square of n so, there is a need to design a binary multiplier which consumes lesser area, power and delay but in general there will be tradeoff between area, power and delay. With the shrinking of technology we can slightly compromise with area. This paper proposes an efficient method for signed binary multiplication using Urdhva-Tiryagbhyam technique, Karatsuba algorithm and efficient carry select adder. Urdhva-Tiryagbhyam technique is known for its low delay [8] as it produces partial products at same instant and sums them up. It is best suited when the number of bits in the multiplier and multiplicand are less than 16 [8], [14]. Whereas Karatsuba algorithm is applicable for multiplication of larger number of bits [5]. The proposed multiplier is implemented for a first stage butterfly unit [12] of a radix-2 FFT algorithm. This proposed design is implemented using Verilog HDL and synthesized in both 90 nm and 45 nm technology at multiplier level and in 45nm technology for butterfly unit using cadence RTL compiler and results are compared.

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2016

Kamatchi S., “An Efficient Design of Low Power Speculatuve Hancarlson Adder Using Concurrent Substraction ”, in ICETET-2016, 2016.

2016

Kamatchi S., “Design of Vedic Multiplier Using Adaptive Hold Logic by Modifying Razor Flipflop”, in ICETET-2016, 2016.

2016

Kamatchi S., “Design And Implementation Of Wireless Communication Based Security System For Railway Purpose Using Fpga ”, in Icctet-2016 And ICETET-2016, 2016.

2016

Kamatchi S., “Reliable Multiplier Design With Adaptive Filter ”, in ICETET-2016, 2016.

Publication Type: Journal Article

Year of Publication Title

2017

Kamatchi S., C. Vivekanandan, and B. Thilagavathi, “Detection and Correction of Multiple Upsets in Memories Using Modified Decimal Matrix Code”, Journal of Computational and Theoretical Nanoscience, vol. 14, pp. 1543-1547, 2017.[Abstract]


When the data's are travelling from one system to another system the radiation in the space environment creates multiple upsets in the memories. These upsets can turn out to be a serious problem in terms of accuracy and performance of the digital system. The reliability of data transmission gets severely affected by these errors. Therefore, it is essential to detect and correct the errors and protect the memories from data corruption. Hamming code can be used to prevent the multiple upsets in memories by error detection and correction. But, the main disadvantage with that Hamming code is that it can correct only single bit error. The other error detection correction code are more complex and requires more area, power and delay, since the encoding and decoding circuits are more complex. The DMC is one type of Error detecting and correcting codes. It requires less area, power, delay and also can be used to detect and correct maximum errors. The DMC has high fault tolerant capability. In the DMC method more redundant bits was required and one combination of error could not be detected and corrected. In this paper redundant bits is reduced and the combination of Error which cannot be detected and corrected by DMC method, can be detected and corrected by Modified DMC method (MDMC) which integrates Electromagnetic Band-Gap (EBG). This MDMC was applied in the cache memory. The information bits are efficiently transmitted through cache memory through bloom filter and Error is detected and corrected by this Modified DMC method (MDMC)

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2016

Kamatchi S., “Design Of Low Power Speculative Han-Carlson Adder”, International Journal For Trends In Engineering And Technology, 2016.

2016

Kamatchi S., “An Improved Aging-Aware Reliable Vedic Multiplier with Novel Adaptive Hold Logic Circuits ”, International Journal of Printing, Packaging & Allied Sciences, 2016.

2015

Kamatchi S. and .C.Vivekanandan, D., “Efficient Aging-Aware Reliable 8-Bit Booth Multiplier with Novel Adaptive Hold Logic Circuit”, International Journal of Applied Engineering Research , vol. 10, no. 39, 2015.[Abstract]


in the current scenario, the development of portable
devices is mounting significantly. As a result, the designers have
to restrict the high power utilization in these portable devices.
Digital multiplication is most predominantly used arithmetic
operations in several ranges of applications like discrete cosine
transform, digital signal processing, and in a variety of scientific
arithmetic circuits. Overall working of the VLSI system is
primarily based on the multiplier. Previously, proposed an agingaware multiplier design with Adaptive Hold Logic (AHL) circuit.
In this scheme, the negative bias temperature instability effect
takes place in case if pMOS transistor undergoes negative bias,
thus increases the delay of the pMOS transistor, and at the same
time considerably reduces the multiplier speed. Accordingly, in
case of positive bias temperature instability takes place when
nMOS transistor undergoes positive bias. Owing to these effects,
transistor speed is reduced and timing violation happens as a
result of system breakdown. Therefore, the circuit is important to
design high performance multipliers for signed multiplication. In
this research work, an aging-aware multiplier design with novel
Adaptive Hold Logic (AHL) circuit proposed with the use of 8-bit
booth multiplier. This multiplier is potential enough to provide
better throughput through the variable latency and can also finetune the AHL circuit to lessen performance degradation,
specifically owing to the aging effect. Furthermore, this
architecture can be implemented to column multiplier, the inputs
to the full adder cells are given by means of utilization of
hardware applied with a condition without buffers. The design of
booth multiplier is capable of providing low power utilization
through AHL circuit and in addition reduces the timing
violations. At last, the experimental results found that the
booth multiplier with AHL can provide low power and delay as
compared to Column bypass multiplier and Column multiplier
without buffer. In addition, the proposed architecture with
column- bypassing multipliers can achieve up to 81.19%
performance improvement as compared with Column bypass
multiplier and Column multiplier without buffer.

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2015

B. Roseline. R and Kamatchi S., “Design of Low Power Asynchronous Parallel Adder ”, International Journal For Scientific Research and Development, vol. 3, pp. 904-908, 2015.[Abstract]


This paper describes an asynchronous parallel adder. It is based on Radix method for faster computation of sum and to reduce delay caused by carry chain. The computation has been carried out using parallel process. The aim of this work is to reduce the Power Delay Product (PDP) and Energy Delay Product (EDP) of an adder. We use two Full Adders (FA) in a single block and use a carry look-ahead technique to shorten the carry path within the radix-4 FA block. To obtain low area, the carry is generated first and then it is reused in sum generation. The adder is implemented using Tanner EDA v13 tool. The practicality and superiority of the proposed technique have been verified by simulations over other asynchronous adders.

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Faculty Research Interest: